1. Rapid Development of a Flexible Validated Processor Model David A. Penry Manish Vachharajani David I. August The Liberty Architecture Research Group Princeton University Dept. of Electrical and Computer Engineering University of Colorado, Boulder

2. 2 Architectural Exploration Want baseline simulator to be validated Want rapid model changes (flexibility) Simulator Architecture Ideas Baseline Simulator

3. 3 Why are flexible, validated simulators hard? Barriers to flexibility Concurrent hardware, but sequential simulators Lack of reuse Validation: 3 kinds of errors [Black & Shen, 98] Specification – knowing what to model Abstraction – deciding how much to model Modeling – doing it right Liberty Simulation Environment addresses flexibility and modeling error through concurrent structural modeling

4. 4 The Itanium 2 11 weeks, 1 designer Systematic, incremental approach EXPRENREGEXEDETWRB Structural Hazard Detection Data Hazard Detection Register Renaming & uOp insertion IPGROT I-BUF Branch Resolution DCU

5. 5 Designing the model: Front-end EXPRENREGEXEDETWRB IPGROT I-BUF 2 weeks1½ weeks Modeling Investigation DCU

6. 6 Designing the model: EXP RENREGEXEDETWRB IPGROT I-BUF ½ day Modeling Investigation DCU EXP

7. 7 Designing the model: REN REGEXEDETWRB IPGROT I-BUF 1 week Modeling Investigation DCU EXPREN

8. 8 Designing the model: Rest of backend IPGROT I-BUF ½ week1 ½ week Modeling Investigation DCU EXPREN REGEXEDETWRB

9. 9 Designing the model: DCU IPGROT I-BUF 1½ weeks2 weeks Modeling Investigation EXPREN REGEXEDETWRB DCU

10. 10 Initial model results

11. 11 Is this good enough? Evaluate effectiveness of instruction prefetching (186.crafty) 0.57113.3%0.647Modified model 8.7%0.5970.649Simulation model 0.623 CPI: Prefetching 2.1%0.636Itanium 2 hardware SpeedupCPI: No Prefetching Model

12. 12 Initial model component analysis

13. 13 Refinements: Front end ROT I-BUF ½ day Modeling Investigation EXPREN REGEXEDETWRB IPG DCU Added prefetch unit

14. 14 Refinements: L1D ROT I-BUF 1 day Modeling Investigation EXPREN REGEXEDETWRB IPG DCU Fix page size Add real hardware page table walk

15. 15 Refinements: Load-use stalls ROT I-BUF 8 days5 days Modeling Investigation EXPREN REGEXEDETWRB IPG DCU Add detailed L2/L3 cache behavior

16. 16 Refined model component analysis

17. 17 Comparison of component errors

18. 18 Refined model results Was 19.8%

19. 19 Uses of the model within our group New pipeline organization with re-cycling of instructions (4 weeks) Rangan, et al. Decoupled Software Pipelining with the Synchronization Array. PACT ’04. (2 weeks) Reis, et al. Design and Evaluation of Hybrid Fault- Detection Systems. ISCA-32. (a few hours to modify, a couple days to learn LSE)

20. 20 Conclusions Liberty Simulation Environment is effective at reducing modeling errors and increasing flexibility To control abstraction and specification errors: Use disciplined refinement: investigate, decide, model Quantitatively verify documents Quantitatively verify abstractions Single metrics are not enough to validate models

21. 21 Backup slides

22. 22 Simulator Construction Systems Reuse simulator infrastructure Architectural Simulator Instance Architecture Description Simulator Builder But still must be able to reuse descriptions Structural composition Medium-grained components Standard communication contracts High parameterizability Separation of concerns

23. 23 This study: Itanium 2 HW complexity ≠ model complexity 11 weeks, 1 designer

24. 24 Liberty Simulation Environment Simulator construction system for high reuse Two-tiered specifications Leaf module templates in C Netlisting language for instantiation and customization Three-signal standard communications contract with overrides (control functions) Code is generated Enable Data Ack

25. 25 Shapes

26. 26 Designing the model EXPRENREGEXEDETWRB IPGROT I-BUF Modeling Investigation DCU