1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 7 - Combinational Logic Spring 2007

2. ECE 425 Spring 2007Lecture 7 - Comb. Logic2 Announcements  Homework due Friday 2/23:  2-2, 2-5, 2-6, 2-7, 2-8, 2-9, 2-12, 2-13, 2-20  Entrance Exam due Friday 2/23  Reading  Wolf 3.1-3.4  Exam 1: Wednesday, March 8

3. ECE 425 Spring 2007Lecture 7 - Comb. Logic3 Where we are...  Last Time:  ASIC Design Standard Cells Gate Arrrays FPGAs  Today:  Combinational Logic Design Static CMOS: Delay, Noise Margin & Power

4. ECE 425 Spring 2007Lecture 7 - Comb. Logic4 Review: Boolean Algebra  Axioms - basic properties assumed to be true  (A1) X= if X≠1(A1’) X=1 if X≠0  (A2) if (X=0) then X’=1(A2’) if (X=1) then X’=0  (A3) 0*0=0(A3’) 1+1=1  (A4) 1*1=1(A4’) 0+0=0  (A5) 0*1=1*0=0(A5’) 1+0=0+1=1  Axioms establish  Possible values (0, 1)  Definitions of operations AND (*), OR (+), NOT(‘)

5. ECE 425 Spring 2007Lecture 7 - Comb. Logic5 Review: Boolean Algebra (cont’d)  Theorems: useful properties proved from axioms  Some example theorems: (T1) X+0=X(T1’) X*1=XIdentities (T2) X+1=1(T2’) X*0=0Null elements (T3) X+X=X(T3’) X*X=XIdempotency (T4) (X’)’=XInvolution (T5) X+X’=1(T4’) X*X’=0Complements (T6) X+Y=Y+X(T6’) X*Y=Y*XCommutativity (T7) (X+Y)+Z=X+(Y+Z)Associativity (T7’) (X*Y)*Z=X*(Y*Z) (T8) X*Y+X*Z = X*(Y+Z)Distributivity (T8’) (X+Y)*(X+Z) = X+Y*Z

6. ECE 425 Spring 2007Lecture 7 - Comb. Logic6 Review: Boolean Algebra (cont’d)  More theorems: (T9) X+X*Y=X(T9’) X*(X+Y)=XCovering (T10) X*Y+X*Y’=XCombining (T10’) (X+UY)*(X+Y’)=X (T11) X*Y + X’*Z + Y*Z = X*Y + X’*ZConsensus (T11’) (X+Y)*(X’+Z)*(Y+Z) = (X+Y)*(X’*Z) (T13) (X+Y)’ = X’ * Y’DeMorgan (T13’) (X*Y)’ = X’ + Y’  For more information:  Consult your logic design (ECE 211-212) notes, or  See a logic design text, such as: J. Wakerly, Digital Design, Principles and Practices 2nd. Ed., Prentice-Hall, 1994

7. ECE 425 Spring 2007Lecture 7 - Comb. Logic7 Logic Expressions  Operators  AND ab = a * b  ORa + b  NANDa | b  XORa  b = a’*b + a*b’  Literals - appearance of input variables  unverted:a  inverted:a'

8. ECE 425 Spring 2007Lecture 7 - Comb. Logic8 Completeness  A set of logical functions is complete if we can generate every possible Boolean function using that set  The set { AND, OR, NOT } is complete  The set { NAND } is complete  The set { AND, OR } is not complete

9. ECE 425 Spring 2007Lecture 7 - Comb. Logic9 Irredundancy  A logical expression is irredundant if no literal can be removed from the expression without changings its value  Redundant expressions: a*b + a a*b + a*b'  Irredundant expressions: a*b' + a'*b a + c*d'

10. ECE 425 Spring 2007Lecture 7 - Comb. Logic10 Minimality  A logic expression is minimal if no equivalent form has a higher cost (i.e., literal count)  Minimality ≠ Irredundancy  CAD tools are available to find the minimal (or near- minimal) form for:  Two level logic (AND/OR Sum of Products)  Multilevel Logic (Arbitrary network of gates)

11. ECE 425 Spring 2007Lecture 7 - Comb. Logic11 Review - Complementary CMOS  Pullup Network - drives output to VDD  Pulldown Network - drives output to GND

12. ECE 425 Spring 2007Lecture 7 - Comb. Logic12 Complementary CMOS Notes  Pullup, pulldown networks should NEVER conduct at same time!  Pullup, pulldown networks are duals  Parallel in pulldown implies serial in pullup  Serial in pulldown implies parallel in pullup  Gate Types:  Simple: NAND, NOR, inverter  And-Or-Invert (AOI)  Or-And-Invert (OAI)

13. ECE 425 Spring 2007Lecture 7 - Comb. Logic13 Layout Considerations  Metal lines required for Vdd!, Gnd!  ndiff, pdiff must be separated by 10 lambda  Transistor options:  horizontal or vertical diffusion lines  Start with minimum-size transistors Increased width implies increased driving capability, but Do the analysis first to see if it’s necessary

14. ECE 425 Spring 2007Lecture 7 - Comb. Logic14 Layout Considerations (cont'd)  Interconnect layers (use vias when necessary):  Metal 1  Metal 2  Poly  Diffusion  Specify a well depending on process type  Use substrate contacts to bias transistors & prevent latchup

15. ECE 425 Spring 2007Lecture 7 - Comb. Logic15 Layout Example - NAND  Compare to Fig 3-10, p. 122  Differences from Magic  Explicit contact cuts  P-tub as well as N-tub  Larger N-well  Note transistor sizes  Note substrate contacts

16. ECE 425 Spring 2007Lecture 7 - Comb. Logic16 Layout Example - NOR  Compare to Fig 3-12, p. 123  Differences from Magic  Explicit contact cuts  P-tub as well as N-tub  Larger N-well  Note transistor sizes  Note substrate contacts

17. ECE 425 Spring 2007Lecture 7 - Comb. Logic17 Layout - Creating Wide Transistors  Divide into multiple transistors  Tie together sources, drains  Compare to Fig 3-9, p. 121  Missing but still needed: substrate contacts

18. ECE 425 Spring 2007Lecture 7 - Comb. Logic18 Review - CMOS Gate Structure

19. ECE 425 Spring 2007Lecture 7 - Comb. Logic19 Inverter - DC Analysis inout A B C D E

20. ECE 425 Spring 2007Lecture 7 - Comb. Logic20 Inverter DC Analysis - Continued A D E B C Source: N. Weste & K. Eshraghian, Principles of CMOS VLSI Design Addison Wesley, 1992 Note dependence on  n /  p Recall:

21. ECE 425 Spring 2007Lecture 7 - Comb. Logic21 Logic Levels: Output  Logic values are represented by a range of voltages  Logic 1: between V OH and V DD (5V)  Logic 0: between V OL and V SS (0V)  Static CMOS Output levels  V OH = V DD (5V)  V OL = V SS = Gnd (0V)

22. ECE 425 Spring 2007Lecture 7 - Comb. Logic22 Logic Levels: Input  Examine DC Input/Output Curve (Fig 3-15, p. 120)  Pick points where slope = -1 as V IL, V IH  Rationale: compare change in V IN, V OUT  V IN < V IL - small change in VIN causes small change in V OUT  V IN > V OUT - small change in VIN causes small change in V OUT  V IN < V IL < V IH - small change in V IN causes large change in V OUT

23. ECE 425 Spring 2007Lecture 7 - Comb. Logic23 Logic Levels - Summary

24. ECE 425 Spring 2007Lecture 7 - Comb. Logic24 Noise Margin  A measure of noise immunity  Logic 1: NM H = V OH - V IH  Logic 0: NM L = V OL - V IL  Important when noise is present  Definition: small random variations in voltage  Don’t want noise to affect circuit output

25. ECE 425 Spring 2007Lecture 7 - Comb. Logic25 V in V out Transistor Sizing and Noise Margin  Changing beta (size) ratio changes V IH, V IL  To balance noise margin:  Make  n =  p => W p =3.5W n  Actually, W p =2W n is often “good enough”

26. ECE 425 Spring 2007Lecture 7 - Comb. Logic26 Coming Up  Delay Calculation  Body effect  Power Consumption  Power-speed product  Parasitics and delay