1. Digital Integrated Circuits© Prentice Hall 1995 Timing ISSUES IN TIMING

2. Digital Integrated Circuits© Prentice Hall 1995 Timing The Clock Skew Problem

3. Digital Integrated Circuits© Prentice Hall 1995 Timing Delay of Clock Wire

4. Digital Integrated Circuits© Prentice Hall 1995 Timing Constraints on Skew

5. Digital Integrated Circuits© Prentice Hall 1995 Timing Clock Constraints in Edge-Triggered Logic

6. Digital Integrated Circuits© Prentice Hall 1995 Timing Positive and Negative Skew

7. Digital Integrated Circuits© Prentice Hall 1995 Timing Clock Skew in Master-Slave Two Phase Design

8. Digital Integrated Circuits© Prentice Hall 1995 Timing Clock Skew in 2-phase design

9. Digital Integrated Circuits© Prentice Hall 1995 Timing How to counter Clock Skew?

10. Digital Integrated Circuits© Prentice Hall 1995 Timing Clock Distribution

11. Digital Integrated Circuits© Prentice Hall 1995 Timing Clock Network with Distributed Buffering

12. Digital Integrated Circuits© Prentice Hall 1995 Timing Example: DEC Alpha 21164

13. Digital Integrated Circuits© Prentice Hall 1995 Timing

14. Digital Integrated Circuits© Prentice Hall 1995 Timing Clock Skew in Alpha Processor

15. Digital Integrated Circuits© Prentice Hall 1995 Timing Self-timed and asynchronous design

16. Digital Integrated Circuits© Prentice Hall 1995 Timing Self-timed pipelined datapath

17. Digital Integrated Circuits© Prentice Hall 1995 Timing Completion Signal Generation

18. Digital Integrated Circuits© Prentice Hall 1995 Timing Completion Signal Generation

19. Digital Integrated Circuits© Prentice Hall 1995 Timing Completion Signal in DCVSL

20. Digital Integrated Circuits© Prentice Hall 1995 Timing Self-timed Adder

21. Digital Integrated Circuits© Prentice Hall 1995 Timing Hand-shaking Protocol

22. Digital Integrated Circuits© Prentice Hall 1995 Timing Event Logic — The Muller C-element

23. Digital Integrated Circuits© Prentice Hall 1995 Timing 2-phase Handshake Protocol

24. Digital Integrated Circuits© Prentice Hall 1995 Timing Example: Self-timed FIFO

25. Digital Integrated Circuits© Prentice Hall 1995 Timing 4-phase Handshake Protocol (or RTZ)

26. Digital Integrated Circuits© Prentice Hall 1995 Timing 4-phase Handshake Protocol - Implementation

27. Digital Integrated Circuits© Prentice Hall 1995 Timing Asynchronous-Synchronous Interface

28. Digital Integrated Circuits© Prentice Hall 1995 Timing A Simple Synchronizer

29. Digital Integrated Circuits© Prentice Hall 1995 Timing Synchronizer: Output Trajectories

30. Digital Integrated Circuits© Prentice Hall 1995 Timing Simulated Trajectory versus One Pole Model

31. Digital Integrated Circuits© Prentice Hall 1995 Timing Mean Time to Failure

32. Digital Integrated Circuits© Prentice Hall 1995 Timing Example

33. Digital Integrated Circuits© Prentice Hall 1995 Timing Cascaded Synchronizers Reduce MTF

34. Digital Integrated Circuits© Prentice Hall 1995 Timing Arbiters

35. Digital Integrated Circuits© Prentice Hall 1995 Timing Synchronization at System Level

36. Digital Integrated Circuits© Prentice Hall 1995 Timing Skew of Local Clocks vs Reference

37. Digital Integrated Circuits© Prentice Hall 1995 Timing Phase-Locked Loop Based Clock Generator

38. Digital Integrated Circuits© Prentice Hall 1995 Timing Ring Oscillator

39. Digital Integrated Circuits© Prentice Hall 1995 Timing Example of PLL-generated clock