1. Microprocessors The MIPS Architecture (Floating Point Instruction Set) Mar 26th, 2002

2. The Notion of Coprocessor A coprocessor is a separate processor that is intimately connected to the main processor and performs separate functions A coprocessor is a separate processor that is intimately connected to the main processor and performs separate functions Originally was a real separate chip Originally was a real separate chip FPT coprocessor on MIPS FPT coprocessor on MIPS 8087 coprocessor (fpt) on original PC 8087 coprocessor (fpt) on original PC Now is usually on the same chip Now is usually on the same chip True of both the 80x86, Pentium and MIPS True of both the 80x86, Pentium and MIPS

3. Coprocessing on MIPS The original idea was a general one The original idea was a general one Up to three coprocessors Up to three coprocessors Specialized functions Specialized functions Well defined interface to processor Well defined interface to processor

4. Coprocessor Instruction Set Load word to coprocessor Load word to coprocessor Store word from coprocessor Store word from coprocessor Move to coprocessor Move to coprocessor Move from coprocessor Move from coprocessor Move control to coprocessor Move control to coprocessor Move control from coprocessor Move control from coprocessor Coprocessor operation Coprocessor operation Branch on coprocessor true Branch on coprocessor true Branch on coprocessor false Branch on coprocessor false

5. Coprocessors on the MIPS There are only two of them There are only two of them System coprocessor System coprocessor Specialized coprocessor instructions Specialized coprocessor instructions Floating-point coprocessor Floating-point coprocessor Floating-point instructions Floating-point instructions

6. Floating-Point Formats Two formats Two formats 32-bit 32-bit 64-bit 64-bit Both these are IEEE formats Both these are IEEE formats Referring to the IEEE-754 standard Referring to the IEEE-754 standard We will deal with details of these formats and the operations required by this standard later. We will deal with details of these formats and the operations required by this standard later.

7. Basic FPT Operations Load and/store from/to the FPA registers Load and/store from/to the FPA registers Moves between FPA and CPU registers Moves between FPA and CPU registers Computational operations Computational operations Add, subtract, multiply, divide Add, subtract, multiply, divide Convert to/from integer Convert to/from integer Floating-point comparisons Floating-point comparisons

8. FP Register Set 32 x 32-bit registers, FPR0-FPR31 32 x 32-bit registers, FPR0-FPR31 Each register can hold 32-bit fpt value Each register can hold 32-bit fpt value Or two adjacent registers can hold 64-bit value (pair must be even/odd, e.g. FPR4/5) Or two adjacent registers can hold 64-bit value (pair must be even/odd, e.g. FPR4/5) Control/Status register Control/Status register Implementation/Revision register Implementation/Revision register

9. Control/Status Register Condition bit from compare instructions Condition bit from compare instructions Exception indication bits Exception indication bits Trap enable bits Trap enable bits Sticky exception bits Sticky exception bits Rounding mode Rounding mode

10. Rounding Modes Round to nearest even Round to nearest even This is the normal default mode This is the normal default mode Round/truncate towards zero Round/truncate towards zero Round down towards minus infinity Round down towards minus infinity Round up towards plus infinity Round up towards plus infinity Last two can be used for interval arithmetic Last two can be used for interval arithmetic

11. Unbiased Rounding Round to nearest exact number Round to nearest exact number For 0.5 case, round so that result is even For 0.5 case, round so that result is even Example for integers Example for integers 2.5 rounds to 2 2.5 rounds to 2 3.5 rounds to 4 3.5 rounds to 4 This avoids bias in rounding This avoids bias in rounding

12. Traps If traps are enabled If traps are enabled Overflow causes a system trap Overflow causes a system trap If traps are not enabled If traps are not enabled Generate infinities Generate infinities Infinities have “normal” arithmetic Infinities have “normal” arithmetic (+infinity) + (+infinity)  (+infinity) (+infinity) + (+infinity)  (+infinity) (+infinity) + (-infinity)  (not-a-number) (+infinity) + (-infinity)  (not-a-number) 1.0 / (-0.0)  (-infinity) 1.0 / (-0.0)  (-infinity)

13. FPT Load/Store Load/Store from memory Load/Store from memory Single precision Single precision Double precision requires two loads/stores Double precision requires two loads/stores Control word Control word Revision control register (load only) Revision control register (load only) Register moves Register moves To/from CPU registers and FP registers To/from CPU registers and FP registers To/from CPU registers and FP control reg To/from CPU registers and FP control reg

14. FPT Computational Instructions Floating add/subtract/multiply/divide Floating add/subtract/multiply/divide Absolute value Absolute value Register move (between fpt regs) Register move (between fpt regs) Negate Negate Convert single to double and vice versa Convert single to double and vice versa Convert to integer format Convert to integer format

15. FPT Comparison Instructions Compare Compare Compares 2 single or double fpt values Compares 2 single or double fpt values Possible tests are all combinations Possible tests are all combinations Normal comparisons Normal comparisons Unordered/ordered comparisons Unordered/ordered comparisons In unordered/ordered comparisons, all comparisons with NaN are false. In unordered/ordered comparisons, all comparisons with NaN are false. For example, unordered or less than or equal For example, unordered or less than or equal If either operand is NaN result is False If either operand is NaN result is False Otherwise result is normal LE Otherwise result is normal LE