1. GROUP MEMBERS TU NGUYEN DINH LE

2. 4 bit Parallel input to serial output (4bit_PISO) shift REG.

3. Design Flow Design specification Schematic capture Create symbol TestBench

4. Design specification Use minimum size of CMOS transistors Use 2input nand gate to create DFF and 4bit PISO. Clock running at 25MHz per cycle = 40n second/cycle. Max. Power is 500 mW Area is no more than 40 mil^2 Number of transistors used = 118 transistors => area = 755.2 micro m^2 Number of 2Nand gates used = 26 Number of Inverter used = 7 Cap_load = 100f F Assume scale factor = 1

5. Schematic capture & Create symbol

7. 2nand_testbench

8. DFF Symbol

9. Internal ckt of DFF

10. DFF_Layout

11. DFF Etracted

12. DFF_Testbench

13. 4bit PISO shift REG.

14. LAYOUT PISO

15. Extracted

16. 4 bit PISO

17. 4bit_PISO_testbench

18. CONCLUSION The project has many errors; the layout of PISO has not done yet. The logic simulation of the PISO has errors We are having a trouble of managing the time (clock) The PISO need to be modified