1. Motivation and Design Issues
Interest in exhibiting advantage of CMOS based digital control
Very low standby power feasible in PFM (low power) mode
Dramatic power saving in PWM mode due to internal power management

2. System Block Diagram Two modes: PWM and PFM digital controller SVDDFB SW
PFM
control
PWM
digital
dither
ring osc.
MUX
soft start counter
ring ADC
clk De Dc
comparator
PVIN
PGND
MODE EN
SGND
SVDD
digital controller
REF
Two modes: PWM and PFM

3. Berkeley Switcher Specifications
Symbol
Parameter
Min
Typ
Max
Units
fsw
Switching Freq
500
1500
kHz
Io,max
Max Output Current mA
VIN
Input Voltage
2.8
5.5 V
Ilim
Switch Peak Current Limit
1000
ΔVADC
PWM Mode ADC Quantization Bin 16 mV
ton
PFM Fixed On-time
1.3 μs
NDPWM
PWM Resolution
5 + 5
Bit
NDITH
PWM Digital Dither Resolution 5
Tsoft-start
Soft start duration
1100
IPFM
Quiescent current in PFM mode 3 μA

4. Power Train Problem: high input voltage vs low voltage process
Solutions:
1. Cascoded stucture
2. Lateral drain extension structure

5. Power Train: Cascoded Structure
Drain
VBias
VIN
Source
VOX
Drain
Source
VOX
VIN
Gate oxide breakdown voltage ~5V
Working voltage ~ 2.5V

6. Power Train: LDD Structure
p-LDD layout
Rdson:
Vgs=1.4V
Vgs=2.5V
n-LDD (Ω)
0.27
0.22
p-LDD (Ω)
1.03
0.51
Measured break down voltage
n-LDD layout
n-LDD: 7.5~8V
p-LDD: 6.5~7.2V
ID (mA)
ID (mA)
VDS (V)
VDS (V)

7. Cascoded Structure Test Results
Rdson:
Rdson:
Vgs=1.4V
Vgs=2.5V
NMOS (Ω)
0.33
0.25
PMOS (Ω)
0.60
0.35
PVIN
PVIN/2
GND
NMOS break down voltage: 7.7V
PMOS break down voltage: 7.9V SW
ID (uA)
VDS (V)

8. Internal Power Management
Scavenges power from gate drive discharge
Offers safe supply voltage for controller circuitry
NFET signal
PVIN
PVIN/2
GND
PFET signal SW
Digital controller
Voltage regulator
80A
40A
40A PWM
Make picture larger to show denotes.

9. Internal Voltage Regulations
PVIN
PGND V
Cext
PVIN
PGND
V/2
Cext
Total current consumptions: 1A
BW of each amplifier: 40kHz

10. Control Law PFM Mode (low power, low quiescent curr.) PWM Mode
Fixed on-time control  avoids ripple jitter due to discrete sampling of comparators at rising Vout in hyst ctrl
ton = 0.8 Tsw = 1.33 s  Vripp,max = 90 Vin = 5.5 V, Iout = 0.1 mA
At high output loads, still jitter due to sampling
PWM Mode
PID control with digital dither
Saturated controller response (for large transients)

11. PFM (Fixed On-time) Mode
Use a table to show power !!!

12. ADC and DPWM Resolution
VADC = 16 mV =  0.8% Vout = 1V
VDPWM = 5.4 Vin = 5.5 V
5 bit ring osc + 5 bit digital dither
no limit cycling in steady state
Sampled at fsw

13. PWM Mode: DPWM Module Isupply Level Shifter Ring-MUX Structure VDDL
PWM off
VDD
VSS
5-bit Differential Ring
5-bit MUX 5
1 pair of differential signals
VDDL
Isupply
Ring-MUX Structure
Level Shifter Dc
Make Isupply denote larger.

14. Protection Mode  Soft Start
Build into digital control loop
Disable PD control
Make error signal slew the digital integrator to the appropriate level corresponding to Vout = Vref
Gain of error signal set to effect desired duration of soft-start sequence, tsoft-start = 1100 s

15. Digital processing core
Int
Fully on
From ringADC De Dc PD
Dc_calc
Go to DPWM
Dither en
Pin: EN
Soft start counter
Soft_start
Fully off
Comb
Logic
Clamp

16. Ring ADC Basics
Frequency of ring oscillator has linear relation with Itot when voltage swing is below threshold:
Simulated oscillator frequency versus supply current
Supply Current (A)
Frequency (Hz)
VDD
Itot
4-stage differential ring oscillator running at sub-threshold current

17. Ring ADC Architecture Σ Digital Block Analog Block
De’
Level
Shifter
CounterN
Counter1 N Σ
VDD
VSS Vo
Vref D1 D2
Analog Block
Digital Block
Remove the equations, but don’t forget to mention them.
Tell that it’s a new design, has not been put in the two application systems yet.
Sampling freq=500kHz, LSB=16mV, approx 100mV window, VDD=1.5V
Measured current: 36.72A, area = 0.15 mm2

18. PFM Mode: Comparator DetailsCK
Vin
Vip
Vop
Von

19. PFM Mode Quiescent Current
Simulation: 600kHz sampling frequency
Comparator, ring osc., level shifters(from ring voltage to internal VDD), and clock generation: 3μA (from PVIN/2)
Internal voltage regulators: 1.0μA(from PVIN)

20. Berkeley Switcher Layout
Ring ADC
DPWM &
Clk Gen
Digi
Core
PFM Mode
Comparator
Power Train
Gate Drives
PFET
NFET
500μm
2.6mm
1.7mm

21. Comparison between Analog and Digital Controllers
For mobile phone application:
Controller
Total Quiescent Current
PFM Mode
PWM Mode (not include power train)
LM2612
150A
550A
Berkeley Switcher (Simulated)
3 A
It’s problematic to compare simulation data with test results. Replace PFM with “quiescent”.
PWMhigh load.
Mismatch of Dc is small compared to power train mismatch in digital case.

22. Berkeley Switcher Pin Description
Pin Number
Pin Name
Function 1 FB
ADC input. Connect directly to Vout 2
REF
Analog voltage reference Vref 3 MP
Internal Voltage Level, mid-point of PVIN & PGND 4
MODE
High for PFM mode
Low for PWM mode 5 EN
Enable Input 6
PGND
Power Ground 7 SW
Switching Node connection to internal PFET & NFET 8
PVIN
Power Supply Input to internal PFET switch 9
SVDD
Signal Supply Input 10
SGND
Analog and Control Ground
Taped-out in Oct 10, 2002, packaged chip returned Jan.20, 2003
Implemented in 0.25um CMOS

23. Personnel and Roles Prof. Seth Sanders, project leader
Jinwen Xiao, PhD student (5th year), leadership on IC designs
Angel Peterchev, PhD student (4rd year), leadership on architecture issues
Kenny (Jianhui) Zhang, PhD student (2nd year), responsibility for power train design

24. Thanks To
Y.C. Liang, visiting Nov.2001~Sep.2002 from Natl. Univ. Singapore, for advising on power train design
Joe Emlano for packaging the chip
It’s problematic to compare simulation data with test results. Replace PFM with “quiescent”.
PWMhigh load.
Mismatch of Dc is small compared to power train mismatch in digital case.