1. 1 Switched Capacitor Circuits for DC-DC Conversion Chi Law Matthew Senesky Nov. 25, 2003

2. 2 Motivation Pro –No magnetic elements –Possible IC implementation Con –Control difficult –Lower power applications More info in Bill and Eddie’s talk

3. 3 Switched Cap Basics Global assumptions (for this presentation) –Circuits are made exclusively from caps, simple switches and sources –Two phase operation with D=0.5 –Constant frequency

4. 4 Fibonacci 5:1 Converter

5. 5 Ideal Capacitor Voltages No-load analysis Goal is to find a consistent set of cap voltages, determine ideal conversion ratio, understand operation In steady-state, no current flow, so voltages are constant Resistance of switches (transistors) is not considered in this part of analysis

6. 6 Conversion Ratio Analysis VC2, VC4: Since V C4 || V C2 in Phase 2, V C4 =V C2 =V out V C3 : By looking at Phase 1, V C3 = V C2 + V C4 = 2V out V C1 : By looking at Phase 2, V C1 = V C2 + V C3 = 3V out V g : By looking at Phase 1, V g = V C1 + V C3 =5V out Thus conversion ratio is 5:1 Note that we have a descending order of Fibonacci number conversion ratio Phase 1: Phase 2:

7. 7 Ideal Currents “Piecewise constant” model Assume: –Current source load –Periodic steady-state operation –Average power balance at input and output (100% efficiency) –Large caps, so approximately constant voltages –Must maintain charge balance

8. 8 Current Analysis Phase 1: Phase 2: I C1 : Assume power balance between input and output. Since C1 is not connected to the source in Phase 2 I C1 = 2I in in Phase 1. I C3 : I C3 = I C1 = 2I in in Phase 2. I C2 : Apply KCL to Phase 1, I C2 = I C1 + I C3 = 4I in I C4 : Need I t =5I in. By KCL on both phases I C4 = I in

9. 9 Output Resistance Need to determine output resistance of circuit to find output voltage and efficiency Case 1: fast switching, only R’s matter –Currents are piecewise DC Case 2: slow switching, only C’s matter –Currents are impulses, get step V changes

10. 10 Fast vs. Slow Switching Currents v o due to currents ioio v2v2 v1v1 vovo iRiR iCiC ioio

11. 11 Fast Switching Currents v o due to currents As i R approaches i o, output resistance approaches R ioio v2v2 v1v1 vovo iRiR iCiC ioio

12. 12 Slow Switching Currents v o due to currents As i C approaches i o, output resistance approaches 0.25T/C ioio v2v2 v1v1 vovo iRiR iCiC ioio

13. 13 Fibonacci 5:1 Converter

14. 14 Fibonacci R OC Analysis Phase 1: Phase 2: Assuming the output impedance is dominated by capacitors, C Φ1 =((C 1 +C 3 )||C 2 )+C 4 C Φ2 =((C 1 ||C 3 )+C 2 )+C 4 The total capacitance is the average of the two phases, C t = (C Φ1 +C Φ2 )/2 R OC = 0.25T/C t

15. 15 Fibonacci R OR Analysis Assuming the output impedance is dominated by resistors, R OR_Φ1 : ((R 1 +R 2 )||R 3 +R 4 +R 5 )||R 6 R OR_Φ2 : ((R 1 +R 2 +R 3 )||R 4 )+R 5 The total output impedance is the average of the two phases, R OR = (R OR_Φ1 +R OR_Φ2 )/2 Phase 1: Phase 2:

16. 16 Fibonacci Results Assume all switch R’s are equal, all C’s are equal R OC =0.25T/(2.08C) R OR =2.2R Results for R=1Ω, C=1 μ F, ƒ sw =5 kHz (slow), 500kHz (fast) Slow switching Fast switching Simulation Hand calculation

17. 17 Design Strategy Simulation Hand calculation R out Optimize R OC and R OR independently for a given area to find component ratios Optimize R OC +R OR for a given area to find ratio of R to C Choose switching frequency where R OR =R OC f sw