1. Implementation of neuronetwork system on FPGA (midterm presentation) supervisor: Karina Odinaev Vyacheslav Yushin Igor Derzhavets Winter 2007.

2. Project definition. 1.Goal: create FPGA based system for string/pattern matching with high code optimization for FPGA structure. 2.The system will have 3 main hardware elements: a.XUPV2P FPGA board. XUPV2P b.DLP-USB245M USB Adapter c.PC with USB port.

3. Done till now: √ √ √ √

4. Application for USB adapter.  The code example from http://www.ftdichip.com/Projects/CodeExamples /VC++.htm was used for reference. http://www.ftdichip.com/Projects/CodeExamples /VC++.htm http://www.ftdichip.com/Projects/CodeExamples /VC++.htm  The special class for handling all required functions for interface with USB adapter was written. – Class constructor load DLL(Dynamic Link Library), initialize all pointers for DLL functions, and open port to USB. –The functions supported by class:  Write  Read  GetStatus of USB stack (not FTDI device – not precise definition in data pages)

5. Connection of USB adapter to FPGA  The J5 slow expansion port was used for connection of USB adapter to XUP board.  J5 pins connected to pins of LVTTL(Low Voltage Logic Threshold Levels ) IO type. → 3.3 V IO must be used.

7. Connection of USB adapter to FPGA USB adapter provide 2 options for connection: 2 nd option has advantage: no need in external power supplier, but the first option was chosen at the end.

8. Connection of USB adapter to FPGA – validation  For validation was chosen the 16th numbers accumulator. (device reads 16 numbers and returns their sum).

9. Connection of USB adapter to FPGA – validation (RTL view)

10. Connection of USB adapter to FPGA – simulation of USB control

11. Current status of neuronetwork  The Model was build and synthesized.  The error from place & route : current design utilize 17K LUTs instead of 13K available on V2P30.  We will go with Inna’s suggestion to utilize BRAMS for part of logic.

12. Time Lines Actual time Estimated time Action 3/1/200727/11/2006 VHDL code ready 15/12/20071/12/2006 API code writing 3/1/20075/12/2006 synthesize the whole project and debug the API -> FPGA input interface ????? 15/12/2006  20/1/2007 make placement optimization (if possible) and run full benchmark for performance validation

15. Input file data Board: http://www.xilinx.com/univ/xupv2p.html USB adapter