1. Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits

2. Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide VHDL enables hardware modeling from the gate level to the system level

3. Combinational Circuit Example 8-line 2-to-1 Multiplexer 8-line 2 x 1 MUX a(7:0) b(7:0) y(7:0) sel sel y 0 a 1 b

4. library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2; An 8-line 2 x 1 MUX a(7:0) b(7:0) y(7:0) sel 8-line 2 x 1 MUX

5. library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2; Entity Each entity must begin with these library and use statements port statement defines inputs and outputs

6. library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2; Entity Mode: in or out Data type: STD_LOGIC, STD_LOGIC_VECTOR(7 downto 0);

7. Standard Logic type std_ulogic is (‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’); -- Don’t care library IEEE; use IEEE.std_logic_1164.all;

8. Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic;

9. architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; Architecture a(7:0) b(7:0) y(7:0) sel 8-line 2 x 1 MUX Note: <= is signal assignment

10. architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; Architecture entity name process sensitivity list Sequential statements (if…then…else) must be in a process Note begin…end in process Note begin…end in architecture

13. An 8-line 4 x 1 multiplexer a(7:0) b(7:0) y(7:0) sel(1:0) 8-line 4 x 1 MUX c(7:0) d(7:0) Sely “00”a “01”b “10”c “11”d

14. An 8-line 4 x 1 multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4 is port ( a: in STD_LOGIC_VECTOR (7 downto 0); b: in STD_LOGIC_VECTOR (7 downto 0); c: in STD_LOGIC_VECTOR (7 downto 0); d: in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (7 downto 0) ); end mux4;

15. Example of case statement architecture mux4_arch of mux4 is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process; end mux4_arch; Must include ALL posibilities in case statement Note implies operator => Sely “00”a “01”b “10”c “11”d

16. VHDL Architecture Structure architecture name_arch of name is begin end name_arch; Signal assignments Concurrent statements Process 1 Process 2 Concurrent statements Processes contain sequential statements, but execute concurrently within the architecture body

17. VHDL Process P1: process (<sensitivity list) begin end process P1; Optional process label Within a process: Variables are assigned using := and are updated immediately. Signals are assigned using <= and are updated at the end of the process.

18. Lab Exercise T1 Multiplexer Simulation using Aldec Active-HDL