1. NuCAD ELECTRICAL ENGINEERING AND COMPUTER SCIENCE McCormick Northwestern University Robert R. McCormick School of Engineering and Applied Science FA-STAC : A framework for fast and accurate static timing analysis with coupling Debasish Das Electrical Engineering and Computer Science Northwestern University Evanston, IL 60208 International Conference on Computer Design, San Jose, CA October 2 nd, 2006

2. June 11, 2015(2) Co-authors Ahmed Shebaita, EECS, Northwestern University Hai Zhou, EECS, Northwestern University Yehea Ismail, EECS, Northwestern University Kip Killpack, Strategic CAD Lab, Intel Corporation Industry Support Cell Library Provider

3. June 11, 2015(3) Outline Previous Research Accurate Coupling Delay Computation Efficient Iteration Mechanism Experimental Setup Conclusions and future work

4. June 11, 2015(4) Previous Research (Coupling Model) Coupling cap dominates interconnect parasitics Miller coupling factor (MCF): switching dependent  Step transitions : (0,2) Sapatnekar et.al, ICCAD 2000  Ramp Models : (-1,3) Kahng et.al, DAC 2000 Chen et.al, ICCAD 2000  Exponetial Models : (-1.885,3.885) Ghoneima et.al, ISCAS 2005 Coupling Model Issues:  Models not extended to Timing Analysis

5. June 11, 2015(5) Previous Research (Static Timing) Timing Analysis with x-cap iterative Iterative analysis with continous models: Chen et.al ICCAD 2000 Iterative analysis with discrete models: Sapatnekar et.al ICCAD 2000, Chen et.al ICCAD 2000, Arunachalam et.al DAC 2000 Iterative analysis issues  Circuit/Coupling structure Ignored  No detailed study of convergence

6. June 11, 2015(6) Salient features  Waveform based accurate coupling model  Efficient iteration scheme (Chaotic Iteration)  Circuit and Coupling structure exploration  Speeding up iteration scheme using structure NuCAD Presents:

7. June 11, 2015(7) Outline Previous Research Accurate Coupling Delay Computation Efficient Iteration Mechanism Experimental Setup Conclusions and future work

8. June 11, 2015(8) Circuit Model Rise/Fall-Delay-Window : (rd l,rd h )/(fd l,fd h ) Rise/Fall-Slew-Window : (rs l,rs h )/(fs l,fs h ) Associated nodes with coupling edge : N1 and N2 NAND CC N1 N2 N3 CC N1 NAND I1 I2 Rise Arc Fall Arc Coupling Edge

9. June 11, 2015(9) Motivational Example Input Delay Rise  I1 : [2,4] I2: [3,5] Input Delay Fall  I1 : [2.5,3.5] I2: [3.5,4.5] Input Slew Rise/Fall  I1: [0.2,0.6] I2 : [0.4,0.8] Average input slew Rise/Fall  I1 : 0.4 I2 : 0.6 Compute initial switching windows: MCF = 1.0 Rise Window : [2.6,5.3] Rise Slew : [0.5,0.7] Rise Window : [3.0,5.8] Rise Slew : [0.6,0.8] MCF = 1.8

10. June 11, 2015(10) Coupling Factor Computation Associated Nodes with coupling edge  Victim Node (V)  Aggressor Node (A)  Static timing seeks for worst bounds Waveform generation on V and A  Overlap ratio (k) computation Overlap ratio is defined as the ratio of aggressor output waveform that overlap with victim threshold voltage  Choose waveforms to generate worst possible k  Effective coupling cap : (1+/- 2k)xCC

11. June 11, 2015(11) Waveform selection Aggressor Victim D o a D o a +t a s D o v D o v +0.5t v s D o v +t v s t t K = 1.0 Victim D o a D o a +t a s D o v D o v +0.5t v s D o v +t v s t t Aggressor K = (D o a +t a s -t v s )/t a s

12. June 11, 2015(12) Waveform selection Aggressor Victim D o a D o a +t a s D o v D o v +0.5t v s D o v +t v s t t Victim D o a D o a +t a s D o v D o v +0.5t v s D o v +t v s t t Aggressor K = (0.5t v s) /t a s K = (D o a +0.5t v s -D o v )/t a s

13. June 11, 2015(13) Waveform Selection Victim D o a D o a +t a s t t D o v D o v +0.5t v s D o v +t v s K = 0 Aggressor Victim D o a D o a +t a s t t D o v D o v +0.5t v s D o v +t v s Aggressor K = 0

14. June 11, 2015(14) Accurate Coupling Delay Computation The idea is ! Compute D and t s from Windows To get bounds (best/worst) on K

15. June 11, 2015(15) Parameter Selection for K computation: Examples

16. June 11, 2015(16) Outline Previous Research Accurate Coupling Delay Computation Efficient Iteration Mechanism Experimental Setup Conclusions and future work

17. June 11, 2015(17) Iteration basics Traditional static timing analysis  Topological order of the circuit Static timing analysis with coupling is ITERATIVE Iterative timing analysis converges to FixPoint  Under a given coupling model (Zhou, ICCAD 2003) Node ordering is important How to make Static Timing Analysis efficient ?  Explore circuit structure for node ordering  Decrease iterations

18. June 11, 2015(18) Clustering Problems in analysis based on topological order  Any update at d  Propagate to e, f, g, h  If update at d not permanent  Calculation wasted Solution: Clustering  Local cluster (B) : Change in e  Changes f  Global cluster (A) : Two interacting local clusters  Timing Analysis  Convergence on clusters Clustering Issues:  With coupling whole circuit can be one global cluster

19. June 11, 2015(19) How to use Clustering ideas ? Coupling edges are bidirectional on Timing Graph Select coupling edges  Timing Graph Acyclic G1 G2 G3 G4 G5 G6 G7 G8 Such coupling edges are called Feedback Edges  Example : Coupling edge with fan-out relation Carry out iterations based on feedback edges CC1 CC2

20. June 11, 2015(20) Feedback Edge Identification Local Coupling Edge  Any change on aggressor should be updated to victim  Update does not occur by fan-out Observation:  Choosing CC1 as local coupling edge Force CC2 to become feedback edge  Choosing CC2 as feedback edge Force CC1 related by fan-out Metric to identify local coupling edge  Coupling Weight = Overlap ratio (K) with 1xCC timing windows G1 G2 G3 G4 G5 G6 G7 G8 CC2 Coupling Edges with no fan-out relation (Local Coupling Edges) CC1

21. June 11, 2015(21) Coupling Partitioning Algorithm Coupling edges are partitioned into:  Feedback edges (Global Coupling Edges)  Local Coupling Edges Algorithm:  Using BFS identify “Easy” Global Edges  Sort remaining coupling edges by coupling weight  Do Identify highest weighted edge (e) as local Find global edges generated by e (g e ) Remove g e from sorted coupling edges  While (no more coupling edges left)

22. June 11, 2015(22) Coupling Partitioning Algorithm (Illustration) G1 G2 G3 G4 G5 G6 G7 G8 CC2 CC1 k CC1 = 0.6, k CC2 = 0.8 G1 G2 G3 G4 G6 G7 G8 CC2 CC1 G5 Local Coupling Edge= CC2 G1 G2 G3 G4 G6 G7 G8 CC1 G5 Super-Node formation G1 G2 G3 G4 G6 G7 CC1 G5 G8 CC1 identified as Global Edge

23. June 11, 2015(23) Coupling Structure Aware Iteration Algorithm Initialization  Add topological sorted nodes in queue  Update coupling capacitance with MCF = 1.0  Update windows on each node Modified Chaotic Iterations  While (queue is not empty) u  Pop a node from queue Update coupling capacitance with new MCFs Update timing windows on u If ( | u old – u new | > ε )  Add fan-out nodes of u to queue  Add nodes to queue coupled by local coupling edges

24. June 11, 2015(24) Outline Previous Research Accurate Coupling Delay Computation Efficient Iteration Mechanism Experimental Setup Conclusions and future work

25. June 11, 2015(25) Circuit Modeling Experiments done on ISCAS85 benchmarks Circuit modeled as DAG (Timing Graph) Nodes in Timing Graph are Gates Edges represent interconnect Nodes are mapped to ASIC logic gates  Faraday 90 nm experimental tech library used  Delay tables are used : f( output load, input slew ) Coupling graph generation  Extracted coupling capacitance values are used  Coupling graph is superimposed on timing graph  Each net is assumed to couple with 4 aggressors

26. June 11, 2015(26) Model Accuracy Results CE denotes number of coupling edges RT : Runtime in seconds, TA : Cell Table Lookup (rd l,rd h ) : Rise delay window 012 Model can be non-conservative !

27. June 11, 2015(27) Performance Enhancement Results CI : Iterative algorithm proposed by Chen et.al Fast-CI : Coupling structure aware algorithm Global : Number of global edges identified P-RT : Coupling partitioning runtime Max = 62.1% Min = 5.7% Average = 26.8%

28. June 11, 2015(28) Outline Previous Research Accurate Coupling Delay Computation Efficient Iteration Mechanism Experimental Setup Conclusions and future work

29. June 11, 2015(29) Conclusions and future work We present FA-STAC  Accurate static timing analysis with coupling  Efficient iteration mechanism to converge faster Novel coupling delay model developed Coupling structure exploited for fast iterations Experimental results on ISCAS benchmarks  Our algorithm give average speed-up of 26.8%  Negligible error in timing windows Future directions  Complex coupling model for local coupling edges Submitted to DATE 2007

30. June 11, 2015(30) THANK YOU Q & A