1. A.R. Hertneky J.W. O’Brien J.T. Shin C.S. Wessels Laser Controller One (LC1) www.teamvice.net

2. January 31, 2006Preliminary Design Review (PDR)2 Outline Background Functionality Block diagrams/sub-systems Parts list/budget Schedule/division of labor Risk analysis

3. January 31, 2006Preliminary Design Review (PDR)3 Background Physics experiments often require laser cooling –Bose-Einstein Condensate (BEC) –atomic fountain clock Laser wavelength locked to hyperfine transition –analog control system –Doppler-free saturated absorption spectroscopy (sat spec)

4. January 31, 2006Preliminary Design Review (PDR)4 Background Establishing/maintaining lock is operator intensive –non-intuitive –manual system monitoring required Incompatible with automated lab equipment

5. January 31, 2006Preliminary Design Review (PDR)5 Functionality Auto-magically scans atomic spectrum Identifies absorption peaks Operator selects a reference peak Configures analog control equipment Lock is engaged

6. January 31, 2006Preliminary Design Review (PDR)6 Functionality A manual operator would… observe erroneous behavior in experiment discover broken lock through troubleshooting repeat procedure to establish lock from scratch Our device will… sense problem recalibrate and reestablish the lock return to normal operation within seconds If the lock is lost

7. January 31, 2006Preliminary Design Review (PDR)7 User Interface Front panel status –LCD available absorption peaks currently selected reference peak time since last lock status change –Two-color LED quick visual: locked/unlocked –Keypad or dial choose peak and initiate automatic behavior

8. January 31, 2006Preliminary Design Review (PDR)8 Hardware Environment

9. January 31, 2006Preliminary Design Review (PDR)9 External Connections

10. January 31, 2006Preliminary Design Review (PDR)10 Hardware Subsystems

11. January 31, 2006Preliminary Design Review (PDR)11 Microcontroller Freescale M683XX Microcontroller Clock speeds for wire wrapped prototype (8-12MHz) and PCB integration (15-20MHz) Integrated Memory Controller LQFP 144, PQFP 132, QFP 144 Packages

12. January 31, 2006Preliminary Design Review (PDR)12 FPGA Module Digilent Spartan-3 Starter Board XC3S1000 Core 1000k gate version 1 Megabyte of SRAM 2 Megabits of platform flash 50 MHz oscillator 3 x 40-pin I/O headers

13. January 31, 2006Preliminary Design Review (PDR)13 Optional FPGA Sub-modules Memory (Flash/SRAM) Test Point Header Serial I/O R2R Module (8-bit DAC up to 25MHz) Two A/D 12-bit converter chips Two D/A 8-bit converter chips RS232 converter Four high bright LEDs 6-pin header to two BNC connectors

14. January 31, 2006Preliminary Design Review (PDR)14 Software/Hardware Division CPU User Interface –LCD Display –Keypad Remote control System management FPGA Laser control interaction Signal processing Application specific functions System monitoring

15. January 31, 2006Preliminary Design Review (PDR)15 Estimated Cost

16. January 31, 2006Preliminary Design Review (PDR)16 Risks and Contingency Plan Risks –unfamiliarity with DSP and control systems –system and algorithmic complexity –integration with automated environment a large task Contingencies –utilize classmates and instructors –modularize and reduce interdependencies –limit project scope

17. January 31, 2006Preliminary Design Review (PDR)17 Schedule

18. January 31, 2006Preliminary Design Review (PDR)18 Project Responsibilities A.R. Hertneky –PCB layout, FPGA development, laser system modifications J.W. O’Brien –System-level software, chassis/UI design, test procedure design J.T. Shin –Analog interfaces, FPGA on-chip peripherals, peripheral simulation C.S. Wessels –Graphical LCD driver, FPGA development, boot loader and CPU firmware

19. January 31, 2006Preliminary Design Review (PDR)19 Thank you. Questions? “I don’t know; and when I know nothing, I usually hold my tongue.” – Creon in Oedipus the King