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Lesson 5 Memory Circuits Electrical Breakdown. Memory.

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Presentation on theme: "Lesson 5 Memory Circuits Electrical Breakdown. Memory."— Presentation transcript:

1 Lesson 5 Memory Circuits Electrical Breakdown

2 Memory

3 EEPROM Layout

4 Psub Ptype Trans Cross section

5 Comparison Density / Si Real estate. Read/Write : capability, cycles #. Non Volatile & Retention. Access time & Random.

6 High Voltages = High Electrical Fields => Breakdown Destructive: Device structure rupture: Insulator, package, metal melt..=>Irreversible damage. Non Destructive: Breakdown of barrier to current flow within the junction.

7 Breakdown Mechanisms Junction Breakdown: a) Avalanche, by Impact ionization. b) Zener BD, by E force on covalently bound electron to free the. Latch-Up: regenerative bipolar-transistor action causes a clamped, low resistance path between VCC and Gnd. Hot Carriers: Injection into the Oxide (fA-pA)=>Modify FET Characteristic. Avalanche Pair Production: Hot Carrier->Avalanche->Hole injection- >Substrate( near drain) in Forward Bias to Source->Electron injection from Source-> More Avalanche. Punch through: Depletion regions for Source and Drain interact to reduce the Barrier for electron flow. Oxide Breakdown:Breakdown strength of SiO 2 insulator:~6*10 7 V/cm

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