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Intel Labs Labs Copyright © 2000 Intel Corporation. Fall 2000 Inside the Pentium ® 4 Processor Micro-architecture Next Generation IA-32 Micro-architecture.

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Presentation on theme: "Intel Labs Labs Copyright © 2000 Intel Corporation. Fall 2000 Inside the Pentium ® 4 Processor Micro-architecture Next Generation IA-32 Micro-architecture."— Presentation transcript:

1 Intel Labs Labs Copyright © 2000 Intel Corporation. Fall 2000 Inside the Pentium ® 4 Processor Micro-architecture Next Generation IA-32 Micro-architecture Doug Carmean Principal Architect Intel Architecture Group August 24, 2000

2 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Agenda IA-32 Processor Roadmap IA-32 Processor Roadmap Design Goals Design Goals Frequency Frequency Instructions Per Cycle Instructions Per Cycle Summary Summary

3 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Intel ® Pentium ® 4 Processor Performance 486 Micro-architecture Time P5 Micro-Architecture P6 Micro-Architecture Today Intel ® NetBurst™ Micro-Architecture

4 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Intel® Pentium® 4 Processor Design Goals Deliver world class performance across both existing and emerging applications Deliver world class performance across both existing and emerging applications Deliver performance headroom and scalability for the future Deliver performance headroom and scalability for the future Micro-architecture that will Drive Performance Leadership for the Next Several Years

5 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Intel® Netburst TM Micro-architecture 400 MHz System BusRapidExecutionEngine Execution Trace Cache Hyper Pipelined Technology AdvancedTransferCache Advanced Dynamic Execution Streaming SIMD Extensions 2 Enhanced Floating Point / Multi-Media

6 Pentium® 4 Processor Block Diagram FP RF FMulFAddMMXSSE FP move FP store 3.2 GB/s System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB StoreAGU LoadAGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB uCodeROM 3 3 Decoder BTB & I-TLB L2 Cache and Control

7 FP RF FMulFAddMMXSSE FP move FP store 3.2 GB/s System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB StoreAGU LoadAGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB uCodeROM 3 3 Decoder BTB & I-TLB Pentium® 4 Processor Block Diagram

8 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 CPU Architecture 101 Delivered Performance = Frequency * Instructions Per Cycle Delivered Performance = Frequency * Instructions Per Cycle FrequencyFrequency

9 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Frequency What limits frequency? What limits frequency? –Process technology –Microarchitecture On a given process technology On a given process technology –Fewer gates per pipeline stage will deliver higher frequency Frequency is driven by Microarchitecture

10 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Netburst TM Micro-architecture Pipeline vs P6 12345678910 FetchFetchDecodeDecodeDecodeRename ROB Rd Rdy/SchDispatchExec Basic P6 Pipeline Hyper pipelined Technology enables industry leading performance and clock rate Hyper pipelined Technology enables industry leading performance and clock rate Basic Pentium ® 4 Processor Pipeline 123456789101112 TC Nxt IP TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF Intro at Intro at  1.4GHz.18µ Intro at Intro at733MHz.18µ

11 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Frequency Time Introduction 233MHz60MHz P5 Micro-Architecture 5 Hyper Pipelined Technology 1.13GHz166MHz P6 Micro-Architecture 10 Today  1.4GHz 20 Netburst Micro-Architecture

12 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 3456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP: Trace cache next instruction pointer Pointer from the BTB, indicating location of next instruction.2 TC Nxt IP 1

13 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 TC Fetch: Trace cache fetch Read the decoded instructions (uOPs) out of the Execution Trace Cache Trace Cache

14 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Drive: Wire delay Drive the uOPs to the allocator

15 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Alloc: Allocate Allocate resources required for execution. The resources include Load buffers, Store buffers, etc..Rename/Alloc

16 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Rename: Register renaming Rename the logical registers (EAX) to the physical register space (128 are implemented).Rename/Alloc

17 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Que:Write into the uOP Queue uOPs are placed into the queues, where they are held until there is room in the schedulers uop Queues

18 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Sch: Schedule Write into the schedulers and compute dependencies. Watch for dependency to resolve.Schedulers

19 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Disp: Dispatch Send the uOPs to the appropriate execution unit.

20 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 RF: Register File Read the register file. These are the source(s) for the pending operation (ALU or other). Integer RF FP RF

21 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Ex: Execute Execute the uOPs on the appropriate execution port.Fop Fms AGU AGU ALU ALU ALU ALU

22 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Flgs:Flags Compute flags (zero, negative, etc..). These are typically the input to a branch instruction.ALU ALU ALU ALU

23 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Br Ck: Branch Check The branch operation compares the result of the actual branch direction with the prediction.ALU ALU ALU ALU

24 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Hyper pipelined Technology FP RF Fop Fms System Interface L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB AGU AGU Schedulers Integer RF ALU ALU ALU ALU Trace Cache Rename/Alloc uop Queues BTB ROM3 3 Decoder BTB & I-TLB L2 Cache and Control 23456789101112 TC Fetch DriveAlloc Rename QueSch Sch Sch 1314 Disp Disp 1516 17 18 19 20 RF Ex Flgs Br Ck Drive Drive RF TC Nxt IP 1 Drive: Wire delay Drive the result of the branch check to the front end of the machine.

25 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 CPU Architecture 101 Delivered Performance = Frequency * Instructions Per Cycle Delivered Performance = Frequency * Instructions Per Cycle Instructions Per Cycle

26 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Improving Instructions Per Cycle Improve efficiency Improve efficiency –Branch prediction –Do more things in a clock Reduce time it takes to do something Reduce time it takes to do something –Reducing latency

27 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Improving Instructions Per Cycle Improve efficiency Improve efficiency –Branch prediction –Do more things in a clock Reduce time it takes to do something Reduce time it takes to do something –Reducing latency

28 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Branch Prediction Dramatic improvement over P6 branch predictor: Dramatic improvement over P6 branch predictor: –8x the size (4K) –Eliminated 1/3 of the mispredictions Proven to be better than all other publicly disclosed predictors Proven to be better than all other publicly disclosed predictors –(g-share, hybrid, etc) Accurate branch prediction is key to enabling longer pipelines Accurate branch prediction is key to enabling longer pipelines

29 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 The Execution Trace Cache L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB Trace Cache 3 3 FP RF FMulFAddMMXSSE FP move FP store 3.2 GB/s System Interface StoreAGU LoadAGU Schedulers Integer RF ALU ALU ALU ALU Rename/Alloc uop Queues BTB uCodeROM Decoder BTB & I-TLB Trace Cache BTB

30 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Execution Trace Cache Advanced L1 instruction cache Advanced L1 instruction cache –Caches “decoded” IA-32 instructions (uops) Removes decoder pipeline latency Removes decoder pipeline latency Capacity is ~12K uOps Capacity is ~12K uOps Integrates branches into single line Integrates branches into single line –Follows predicted path of program execution Execution Trace Cache feeds fast engine

31 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 1 cmp 2 br -> T1....... (unused code)... (unused code) T1: 3 sub 4 br -> T2 4 br -> T2....... (unused code)... (unused code) T2: 5 mov 6 sub 6 sub 7 br -> T3 7 br -> T3....... (unused code)... (unused code) T3: 8 add 9 sub 9 sub 10 mul 10 mul 11 cmp 11 cmp 12 br -> T4 12 br -> T4 Execution Trace Cache Trace Cache Delivery 10 mul 11 cmp 12 br T4 7 br T3 8 T3:add 9 sub 4 br T2 5 mov 6 sub 1 cmp 2 br T1 3 T1: sub

32 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Advanced Dynamic Execution Provides larger window of visibility Provides larger window of visibility –Better use of execution resources Deep Speculation Improves Parallelism Extends basic features found in P6 core Extends basic features found in P6 core Very deep speculative execution Very deep speculative execution –126 instructions in flight (3x P6) –48 loads (3x P6) and 24 stores (2x P6)

33 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Improving Instructions Per Cycle Improve efficiency Improve efficiency –Branch prediction –Do more things in a clock Reduce time it takes to do something Reduce time it takes to do something –Reducing latency

34 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Rapid Execution Engine P4P: P4P: –½ clock @ >1.4GHz <0.36ns 1ns Dramatically lower ALU latency Dramatically lower ALU latency P6: P6: –1 clock @ 1GHz

35 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 L1 Data Cache L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB Trace Cache 3 3 FP RF FMulFAddMMXSSE FP move FP store 3.2 GB/s System Interface StoreAGU LoadAGU Schedulers Integer RF ALU ALU ALU ALU Rename/Alloc uop Queues BTB uCodeROM Decoder BTB & I-TLB L1 D-Cache and D-TLB L1 D-Cache and D-TLB

36 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 High Performance L1 Data Cache 8KB, 4-way set associative, 64-byte lines 8KB, 4-way set associative, 64-byte lines Very high bandwidth Very high bandwidth –1 Ld and 1 St per clock New access algorithms New access algorithms Very low latency Very low latency –2 clock read New algorithm enables faster cache

37 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Observation: Almost all memory accesses hit in the cache Observation: Almost all memory accesses hit in the cache Optimize for the common case Optimize for the common case –Assume that the access will hit the cache –Use a low cost mechanism to fix the rare cases that miss Benefit: Benefit: –Reduces latency –Significantly higher performance Data Speculation

38 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Replay Repairs incorrect speculation Repairs incorrect speculation –Re-execute until correct Replay is uOP specific Replay is uOP specific –Replay the uOP that mis-speculated –Replay dependent uOPs –Independent uOPs are not replayed

39 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 L1 Cache is >2x Faster P4P: P4P: –2 clocks @  1.4GHz Lower Latency is Higher Performance 3ns <1.4ns P6: P6: –3 clocks @ 1GHz

40 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Example with Higher IPC and Faster Clock! CodeSequence Ld Ld Add Add Ld Ld Add Add 10 clocks 10ns IPC = 0.6 6 clocks 4.3ns IPC = 1.0 P6@1GHz Pentium® 4 Processor@1.4GHz

41 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 L2 Advanced Transfer Cache L2 Cache and Control L1 D-Cache and D-TLB L1 D-Cache and D-TLB Trace Cache 3 3 FP RF FMulFAddMMXSSE FP move FP store 3.2 GB/s System Interface StoreAGU LoadAGU Schedulers Integer RF ALU ALU ALU ALU Rename/Alloc uop Queues BTB uCodeROM Decoder BTB & I-TLB L2 Cache and Control

42 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 L2 ATC Organization 256KB, 8-way set associative 256KB, 8-way set associative –128-byte lines –Two 64-byte pieces per line Holds both data and instructions Holds both data and instructions High bandwidth: 45 GB/Sec @ 1.4GHz High bandwidth: 45 GB/Sec @ 1.4GHz –2.8x P6 @1GHz

43 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Aggregate Cache Latency Function of all caches in a processor Function of all caches in a processor Overall Effective Latency Overall Effective Latency L1 latency + L1 Miss Rate * L2 latency + L2 Miss Rate * DRAM Latency Average cache speed is >1.8x better than the Pentium ® III Processor! Average cache speed is >1.8x better than the Pentium ® III Processor! Average on desktop applications, Pentium ® III Processor @ 1GHz, Pentium ® 4 Processor @ 1.4GHz

44 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Pentium ® III Processor Pentium ® 4 Processor RelativeImprovement Frequency 1 GHz > 1.4 Ghz > 1.4 Adder Speed 1 ns <.36 ns > 2.8 L1 Cache Speed 3 ns < 1.42 ns > 2.1 L1 Cache Size 16 KB 8 KB 0.5 L1 Cache Bandwidth 16 GB/sec > 44.8 GB/sec > 2.8 L2 Cache Bandwidth 16 GB/sec > 44.8 GB/sec > 2.8 Uop Fetch Bandwidth 3 billion/sec > 4.2 billion/sec > 1.4 Adder Bandwidth 2 billion/sec > 5.6 billion/sec > 2.8 Branch targets 51240928 Instructions In flight 401263.15 Loads in flight 16483 Stores in flight 12242Recap

45 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000 Intel® Pentium® 4 Processor Summary Revolutionary, new micro- architecture from Intel designed for the evolving Internet Revolutionary, new micro- architecture from Intel designed for the evolving Internet Design features for balanced, high performance platform scalability and headroom Design features for balanced, high performance platform scalability and headroom The world’s highest performance desktop processor The world’s highest performance desktop processor

46 Intel PDX PDX Copyright © 2000 Intel Corporation. Fall 2000

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