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CS 140 Lecture 17 Professor CK Cheng 11/26/02
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System Designs 1.Intro 2.Spec 3.Implementation
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Given an algorithm, produce the data and control subsystems Algorithm: { Input X, Y type bit-vector, start type boolean; Local-Object A, B type bit-vector; Output Z type bit-vector, done type boolean; Wait: If start’ goto Wait; S1: A X || B Y|| done 0; S2: If B >= 0 goto S4; S3: B -B; S4: If A >= B goto S6; S5: A A + 1 || B B-1 || goto S4; S6: Z 4 * A || done 1 || goto Wait; }
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Data Subsystem Control Subsystem C 1-7 (A > B)B7B7 X Y start Z done Z = 4 Ceiling[ (X + |Y| )/ 2] if X< |Y| 4X otherwise 8 8 8
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A X B Y B -B A >= B A A + 1 B B – 1 Z 4A operation A Load (X) B Load (Y) B CS (B) Comp (A, B) A INC (A) B DEC (B) Z Load (A) Z SHL (Z) control C 1 C 2 C 3 C 4 C 5 C 6 C 7
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B A C2C2 C3C3 C5C5 C1C1 C4C4 X INC Comp Z Control Unit B C6C6 C7C7 CS DEC Y C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 start done
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S0: S1: S2: S3: S4: S5: S6: S7: S8: If start’, goto S0, else goto S1 A X || B Y || done 0 || goto S2 If B’ goto S4, else goto S3 B CS (B), goto S4 If k goto S6, else goto S5 A INC (A), B DEC (B), goto S4 Z A goto S7 Z SHL (z), goto S8 Z SHL (z), done 1, goto S0 Designing the control unit
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State Machine S0 S1 S2 S3 S4 S8 S7 S6 S5 k’ k B B’ start’ start
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start’ S2 S3 B7B7’ S5 S6 S0 S1 S4 k k’ S7 S8
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