1. 6/11/2015 Adaptive Hardware Design for Digital Signal Processing Advisor: Dr. Thomas L. Stewart By: Prabjot Kaur Alex Tan

2. 6/11/2015 Presentation Outline q Project Goal q Project Description tFunctional Description tBlock Diagram q Changes q Main Problem q Solution q Design Approaches q Schedule

3. 6/11/2015 Project Goal t Design a Digital Signal Processing (DSP) hardware device t Implemented With Field Programmable Gate Arrays (FPGAs). t Investigate the capability of FPGAs to perform different functions through reconfigurations of the hardware design.

4. 6/11/2015 Project Description Functional Description: DSP is the process of manipulating a digital input. This process utilizes multipliers and adders to achieve this. Typical Equation: y(n) = a 1 *y(n-1)+a 2 *y(n-2)+......a m *y(n-m)+b*x(n)

5. 6/11/2015 Project Description Functional Description contd. x(n): 8 or 16 bit 2’s complement word Control Switch: Precision of the DSP function to be implemented y(n): The result of the DSP function. FPGA DSP Implementation input x(n) output y(n) Control Switch

6. 6/11/2015 Changes t VHDL

7. 6/11/2015 FA A3Bo A1B1 A2B2AoB3 So S1 S2S3 CoC1 C2 C3 C4 4-Bit Ripple Carry Adder * n-bit ripple carry adder will have 2n+2 gate delay Main Problem

8. 6/11/2015 ALTERNATIVE: Carry Lookahead Adder (CLA) n Required to build a Partial Full Adder (PFA) Separates the parts of the full adder not involving the carry propagation path from those containing the path. Solution

9. 6/11/2015 Xilinx Feature S G P C PFA Block BA

10. 6/11/2015 Carry Lookahead Adder (CLA)

11. 6/11/2015 Comparison GATE DELAYS: CLARCA 4-bit adder6 gates10 gates 16-bit adder10 gates34 gates 64-bit adder14 gates120 gates

12. 6/11/2015 4Build and test an 8-bit adder n16-bit adder and multiplier nImplementation into an FPGA nBuild and test memory cells and registers nComplete an 8-bit and a 16-bit DSP chip nReconfigure the FPGA between real time 8-bit and 16-bit DSP processing Design Approaches

13. 6/11/2015 Schedule Work Time: Jan. 24 - April 15, 2000 Four main parts: 4 2 weeks : Research and Learning t 3 weeks : Design and Building (more emphasis on Design) t 3 weeks : Design and Building (more emphasis on Building) t 3 weeks : Testing and recording Data t Time after April 15: Testing and getting ready for demo.

14. 6/11/2015 Thank You! Any Questions? Any Questions?