Presentation is loading. Please wait.

Presentation is loading. Please wait.

CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch. 7.1-7.5) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch. 7.1-7.5) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation."— Presentation transcript:

1 CS 140 Lecture 7 Professor CK Cheng 4/23/02

2 Part II. Sequential Network (Ch. 7.1-7.5) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation Characteristic Eq. Q(t+1) = f(x, Q(t)).

3 SR Flip-Flop (Set-Reset) S R S R y Q Q = (R+y)’ y = (S+Q)’

4 Id Q y S R y* Q* y** Q** y*** Q*** 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 0 2 0 0 1 0 0 1 0 1 0 1 3 0 0 1 1 0 0 0 0 0 0 4 0 1 0 0 1 0 1 0 1 0 5 0 1 0 1 1 0 1 0 1 0 6 0 1 1 0 0 0 0 1 0 1 7 0 1 1 1 0 0 0 0 0 0 8 1 0 0 0 0 1 0 1 0 1 9 1 0 0 1 0 0 1 0 1 0 10 1 0 1 0 0 1 0 1 0 1 11 1 0 1 1 0 0 0 0 0 0 12 1 1 0 0 0 0 1 1 0 0 13 1 1 0 1 0 0 1 0 1 0 14 1 1 1 0 0 0 0 1 0 1 15 1 1 1 1 0 0 0 0 0 0 Q y State Transition SR 10 00 11 00 10 SR 11 10 01 11 01 11 01 1000 10 00 01 00 11 State Diagram 01

5 When SR=01, (Q,y) = (0,1) When SR=10, (Q,y) = (1,0) When SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps changing Solutions: 1) SR = (0,0). 2) SR = (1,1). 0 0 0 1 - 1 1 0 1 - PS inputs 00 01 10 11 State table Q(t+1) SR Characteristic Eq Q(t+1) = S(t)+R’(t)Q(t)

6 D Flip-Flop (Delay) D CLK Q Q’ Id D Q(t) Q(t+1) 0 0 0 1 1 0 2 1 0 1 3 1 1 - Characteristic Eq Q(t+1) = D(t) 0 0 1 1 0 1 PS D 0 1 State table Q(t+1)

7 JK F-F J CLK Q Q’ Characteristic Eq Q(t+1) = Q(t)K’(t)+Q’(t)J(t) 0 0 0 1 1 1 1 0 1 0 PS JK 00 01 10 11 State table Q(t+1) K

8 T Flip-Flop (Toggle) T CLK Q Q’ Characteristic Eq Q(t+1) = Q’(t)T(t) + Q(t)T’(t) 0 0 1 1 1 0 PS T 0 1 State table Q(t+1)

Download ppt "CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch. 7.1-7.5) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation."

Similar presentations

CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.
CS 140 Lecture 10 Sequential Networks: Implementation Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 10 Sequential Networks: Implementation Professor CK Cheng CSE Dept. UC San Diego 1.
1 Lecture 14 Memory storage elements  Latches  Flip-flops State Diagrams.

1 Lecture 14 Memory storage elements  Latches  Flip-flops State Diagrams.
Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.

Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.
CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi

CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi
Sequential Logic Latches and Flip-Flops. Sequential Logic Circuits The output of sequential logic circuits depends on the past history of the state of.

Sequential Logic Latches and Flip-Flops. Sequential Logic Circuits The output of sequential logic circuits depends on the past history of the state of.
Digital Electronics Chapter 5 Synchronous Sequential Logic.

Digital Electronics Chapter 5 Synchronous Sequential Logic.
1 Sequential Systems A combinational system is a system whose outputs depend only upon its current inputs. A sequential system is a system whose outputs.

1 Sequential Systems A combinational system is a system whose outputs depend only upon its current inputs. A sequential system is a system whose outputs.
1 Chapter 8 Flip-Flops and Related Devices. 2 Figure 8--1 Two versions of SET-RESET (S-R) latches S-R (Set-Reset) Latch.

1 Chapter 8 Flip-Flops and Related Devices. 2 Figure 8--1 Two versions of SET-RESET (S-R) latches S-R (Set-Reset) Latch.
Nonlinear & Neural Networks LAB. CHAPTER 11 LATCHES AND FLIP-FLOPS 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop.

Nonlinear & Neural Networks LAB. CHAPTER 11 LATCHES AND FLIP-FLOPS 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop.
Logical Circuit Design Week 11: Sequential Logic Circuits Mentor Hamiti, MSc Office 305.02,

Logical Circuit Design Week 11: Sequential Logic Circuits Mentor Hamiti, MSc Office ,
1 Sequential Circuits Dr. Pang. 2 Outline Introduction to sequential circuits Basic latch Gated SR latch and gated D latch D flip-flop, T flip-flop, JK.

1 Sequential Circuits Dr. Pang. 2 Outline Introduction to sequential circuits Basic latch Gated SR latch and gated D latch D flip-flop, T flip-flop, JK.
Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.

Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.
CS 140L Lecture 5 Professor CK Cheng 4/29/02. Asynchronous Counter D Q CLK D Q D Q There are n flip-flops. D FF is the delay of each flip-flop. When n.

CS 140L Lecture 5 Professor CK Cheng 4/29/02. Asynchronous Counter D Q CLK D Q D Q There are n flip-flops. D FF is the delay of each flip-flop. When n.
CS 140 Lecture 9 Professor CK Cheng 4/30/02. Part II. Sequential Network 1.Memory 2.Specification 3.Implementation S XY s i t+1 = g i (S t, x t )

CS 140 Lecture 9 Professor CK Cheng 4/30/02. Part II. Sequential Network 1.Memory 2.Specification 3.Implementation S XY s i t+1 = g i (S t, x t )
CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )

CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )
CSE 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego 1.

CSE 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego 1.
CS 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.
CS 140 Lecture 10 Professor CK Cheng 5/02/02. Given the state table, implement with 2 JK flip flops id 0 1 2 3 4 5 6 7 Q 1 (t) 0 1 Q 0 (t) 0 1 0 1 X(t)

CS 140 Lecture 10 Professor CK Cheng 5/02/02. Given the state table, implement with 2 JK flip flops id Q 1 (t) 0 1 Q 0 (t) X(t)
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.

CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.

Similar presentations

Ads by Google