1. Problem 1 Defining Netlist Snarl Factor

2. Some Background A B C D F G EH A B C D F G EH Congested area PlacementRouting A B C D F G E H Netlist == Graph Blocks (e.g. AND,OR) Wires Inputs Outputs NB: Netlists are big ! > 4e7 blocks

3. Problem: Predicting Congestion Predicting wire length, area early is essential –How fast will the chip go ? –How big must the chip be to allow all wires ? Under predicting wires leads to congestion –Congested areas cannot be routed –The chip is in trouble Can we define a better means of predicting congestion before placement and routing ? Specifically can we define a localized connectivity metric and use it to partition a netlis

4. Real life congestion examples Congested area What we often getWhat we want

5. Snarl Some netlists are easy to ‘un-snarl’ Simple left to right logic No / few loops Uniform, low fan-out Statistical models work Easy to place and route Some netlists are very difficult E.g. ‘Crossbar Switches’ Many loops NB: not simple cycles or cliques Non-uniform fan-out Statistical models don’t work Difficult to place and route

6. Internal Rents Rule Used to predict the connectivity of ideal uniform netlists P = T B B R Where P= number of external connections to the partition T B = average pins per block B= number of blocks R= Rent’s exponent Think Gauss’s Law AA AAA A T B =2 R=0 A A A AA A AAA A A A A A T B =4 R=0.5

7. Typical Rent’s Coefficients TBTB R Memory61.2 Gate Array1.90.5 Processor1.40.63 Circuit board820.25 Ref: http://www.cedcc.psu.edu/ee497i/rents_rule.PDF

8. Challenge Rent’s rule is used to predict connectivity of uniform netlists using empirical coefficients Can we create a similar figure of merit metric on real, non-uniform netlists ? Can we also localize the metric to portions of the netlist ?

9. Example of New Metric U1U1 U2U2 U3U3 Where U 3 < U 1 < U 3 U overall = ƒ(U 1, U 2, … U n )

10. Possible Applications Early identification of ‘difficult’ netlists Early guidance towards netlist improvement Better allocation of additional routing space

11. Problem 2 Geometric Pattern Recognition

12. Some Background Chips built up of many layers Process similar to silkscreen Devices composed of unique combinations of layer and geometry Many steps analyze these geometric interactions –Manufacturability checks –Device and wire extraction –Yield calculations, etc. Polysilicon gateDiffusion Contact cuts

13. Problem: Finding Layout Patterns Geometric interactions are quite complex –Modern chips have > 1e9 shapes –Some inter layer interactions matter, others do not –Relative geometric arraignment matters –Size and orientation (usually) do not –Most, but not all, shapes are rectilinear polygons Methods exist to find general interactions by coding increasingly selective filters, but they are inexact and labor intensive Can we define an efficient way to find all instances of a specific example sub-layout ?

14. Example: pattern recognition Find all occurrences of the sample layout in the chip

15. Challenge What geometric representation best captures unique interactions between shapes ? Can we find a representation that is invariant wrt. scaling and rotation ? Can we find such a representation that can be searched very efficiently ?

16. Ideas Can we transform both the chip geometry and the pattern into a graph of some type, then use sub- graph isomorphism techniques to identify the matches ? If so ? What type of graph ? E.g Constraint graph.. X-graphY-graphHow to couple X,Y ?

17. Possible Applications Optical proximity correctionLayout migration Without OPC With OPC