1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 9 - Combinational Logic Design - Other Logic Families Spring 2007

2. ECE 425 Spring 2007Lecture 9 - Comb. Logic2 Announcements  Homework Due Mon. Mar. 5  3-1, 3-4, 3-6, 3-7, 3-14, 3-16  Reading  3.1-3.7  Exam 1: Scheduled for Wed. March 7

3. ECE 425 Spring 2007Lecture 9 - Comb. Logic3 Where we are...  Last Time:  Combinational Logic - Static CMOS (cont’d) Transistor Sizing Power Dissipation  Today:  Combinational Logic - Static CMOS (cont’d) Power-Speed Product Parasitics and Performance Other CMOS Logic Families

4. ECE 425 Spring 2007Lecture 9 - Comb. Logic4 Switch Logic  Key idea: use transistors as switches  Concern: switches are bidirectional AND OR

5. ECE 425 Spring 2007Lecture 9 - Comb. Logic5 Switch Logic - Pass Transistors  Use n-transistor as “switches”  “Threshold problem”  Transistor switches off when V gs < V t  V DD input -> V DD -V t output  Special gate needed to “restore” values IN: V DD A: V DD OUT: V DD -V tn

6. ECE 425 Spring 2007Lecture 9 - Comb. Logic6 Switch Logic - Transmission Gates  Complementary transistors - n and p  No threshold problem  Cost: extra transistor, extra control input  Not a perfect conductor! A A’ A

7. ECE 425 Spring 2007Lecture 9 - Comb. Logic7 Switch Logic Example - 2-1 MUX IN

8. ECE 425 Spring 2007Lecture 9 - Comb. Logic8 Effective Resistance in Trans. Gates  Transmission Gate is not a perfect switch  Effective Resistance: p, n in parallel Graphic Source: J. Rabaey, Digital Integrated Circuits © Prentice-Hall 1995

9. ECE 425 Spring 2007Lecture 9 - Comb. Logic9 Approximating Req in Trans. Gates  Approximation from Rabaey’s Book:  Assume both transistors in linear mode  Let V A = voltage on input node  Let V B = voltage on output node

10. ECE 425 Spring 2007Lecture 9 - Comb. Logic10 Charge Sharing  Consider transmission gates in series  Each node has parasitic capacitances  Problems occur when inputs change to redistribute charge  Solution: design network so there is always a path from V DD or Gnd to output

11. ECE 425 Spring 2007Lecture 9 - Comb. Logic11 Aside: Transmission Gates in Analog  Transmission Gates work with analog values, too!  Example: Voltage-Scaling D/A Converter

12. ECE 425 Spring 2007Lecture 9 - Comb. Logic12 Aside - Discuss Labs 5-7  Digital-Analog Conversion - Common Approaches  Current-Scaling Binary-Scaled R2R network  Voltage-Scaling Resistor-String Folded Resistor String  Charge-Scaling  Oversampling Converters

13. ECE 425 Spring 2007Lecture 9 - Comb. Logic13 Review: R-2R D/A  You built one of these in Circuits lab

14. ECE 425 Spring 2007Lecture 9 - Comb. Logic14 D/A Conversion - Voltage Scaling

15. ECE 425 Spring 2007Lecture 9 - Comb. Logic15 Labs 5-7 - Voltage-Scaling D/A Converter

16. ECE 425 Spring 2007Lecture 9 - Comb. Logic16 Labs 5-7: Hierarchical Layout Design  Use hierarchy and regularity to reduce layout effort  Basic cell: resistor + transmission gate  Column cell: combines four basic cells  Complete array: Four column arrays Row decoder Column multiplexer

17. ECE 425 Spring 2007Lecture 9 - Comb. Logic17 Hierarchical Stick Diagram - D/A

18. ECE 425 Spring 2007Lecture 9 - Comb. Logic18 Lab 5 - DAC Array Layout Odd Columns Even Columns

19. ECE 425 Spring 2007Lecture 9 - Comb. Logic19 Lab 5 - DAC Array Layout  An example of hierarchical layout:  Leaf cells:  RPTA - Resistor + Transmission Gate  RPTB - Resistor + Transmission Gate (resistor above)  Intermediate cell:  colA - contains four RPTA, col_connect  colB - contains four RPTB  Root cell:  dac_array - contains 2 colA, 2 colB + connecting wires

20. ECE 425 Spring 2007Lecture 9 - Comb. Logic20 Lab 5 - Additional Layout Concerns  Leaf cells  Create resistor RPT cell using poly, polycontacts  Connect basic inputs, outputs by abutment  Connect n-wells by abutment  Include Vdd!, Gnd!, and substrate contacts in each leaf cell  Intermediate cells  Provide m1 connections for Vdd!, Gnd! with no jumpers  Connect resistor chain RPT, PT, cells with no jumpers (beyond those required for resistors)

21. ECE 425 Spring 2007Lecture 9 - Comb. Logic21 Lab 6 - Completing the DAC Layout  Design Row Decoder & Add to Hierarchy  Leaf cells: NAND gates, inverters, XOR gates  Match outputs to row select lines  Design Column Multiplexer  Use row decoder + transmission gates (modify if necessary)  Match inputs to column output lines  Final result:  4 digital inputs d3, d2, d1, d0  1 analog output: OUT

22. ECE 425 Spring 2007Lecture 9 - Comb. Logic22 Lab 7 - Verifying the DAC  Modify RPT cell to “mark” resistor for extraction :paint rpoly  Extract circuit & make Spice deck :extract all :ext2spice DAC  Simulate using PSPICE and verify output for all 16 input values (0000 - 1111)

23. ECE 425 Spring 2007Lecture 9 - Comb. Logic23 NMOS Logic  Used before CMOS was widely available  Uses only n transistors  Normal n transistors in pull-down network  depletion-mode n transistor (V t < 0) used for pull-up  "ratioed logic" required  Tradeoffs: +Simpler processing +Smaller gates -higher power! -Additional design considerations for ratioed logic Passive Pullup Device: depletion Mode n-transistor (V t < 0) OUT Pulldown Network

24. ECE 425 Spring 2007Lecture 9 - Comb. Logic24 Pseudo-nmos Logic  Same idea, as nmos, but use p- transistor for pullup  "ratioed logic" required for proper design (more about this next)  Tradeoffs: +Fewer transistors -> smaller gates, esp. for large number of inputs +less capacitative load on gates that drive inputs –larger power consumption –less noise margin (V OL > 0) –additional design considerations due to ratioed logic Passive Pullup Device: P-Transistor OUT Pulldown Network

25. ECE 425 Spring 2007Lecture 9 - Comb. Logic25 Ratioed Logic for Pseudo-nmos  Approach:  Assume V OUT =V OL =0.25*V DD  Assume 1 pulldown transistor is on  Equate currents in p, n transistors  Solve for ratio between sizes of p, n transistors to get these conditions  Further calculations necessary for series connections I dp OUT Pulldown Network I dn

26. ECE 425 Spring 2007Lecture 9 - Comb. Logic26 DCVS Logic  DCVS - Differential Cascode Voltage Switch  Differential inputs, outputs  Two pulldown networks  Tradeoffs +Lower capacitative loading than static CMOS +No ratioed logic needed +Low static power consumption -More transistors -More signals to route between gates -Example: Fig. 3.29 p. 148 OUT Pulldown Network OUT’ OUT’ Pulldown Network OUT A B C A’ B’ C’

27. ECE 425 Spring 2007Lecture 9 - Comb. Logic27 Pulldown Network CSCS   A B C Dynamic Logic  Key idea: Two-step operation  precharge - charge C S to logic high  evaluate - conditionally discharge C S  Control - precharge clock  Storage Node Storage Capacitance Precharge Signal PrechargeEvaluatePrecharge

28. ECE 425 Spring 2007Lecture 9 - Comb. Logic28 Domino Logic  Key idea: dynamic gate + inverter  Cascaded gates - “monotonically increasing” Pulldown Network CSCS   B C  in4 x1 x2 x3

29. ECE 425 Spring 2007Lecture 9 - Comb. Logic29 Domino Logic Tradeoffs +Fewer transistors -> smaller gates +Lower power consumption than pseudo-nmos -Clocking required -Charge sharing can be an issue (see Fig. 3.34) -Logic not complete (AND, OR, but no NOT)

30. ECE 425 Spring 2007Lecture 9 - Comb. Logic30 Coming Up:  Low-Power Gates  Wire Delays, Buffering, and Sizing  Combinational Logic Networks