1. Redesign control FSM of a multicycle MIPS processor with low power state encoding

2. Introduction Mealy and Moore FSMs

3. Introduction MultiCycle MIPS controller is actually a moore FSM

4. Random Encoding 0000 (0) 1010 (10) 1001 (9) 1000 (8) 0010 (2) 0011 (3) 0100 (4) 0101 (5) 0110 (6) 0001 (1) Fetch lw, sw lw sw R B J Decode 0111 (7) Exception 1 1 21 3 2 1 2 23 223 1 22

5. Optimized encoding 0000 (0) 0010 (2) 0100 (4) 0110 (6) 0111 (7) 0101 (5) 0011 (3) 1000 (8) 1001 (9) 0001 (1) Fetch lw, sw lw sw R B J Decode 1010 (10) Exception 1 1 1 21 3 1 1 11 122 2 1 1

6. Encoding Algorithm Finding absolute optimal state encoding is NP hard, but there are some huristics: One Level Tree (OLT) [1] POW3 [2] Spanning Tree Based (STB) WCEC (Weakly Crossed Edge Cuts Ecoding) [1] Baccheta P., L. Daldoss, D. Sciuto and C. Silvano, “Lower- Power State Assignment Techniques for Finite State Machines”, IEEE International Symposium on Circuits and Systems (ISCAS’00), 2000, pp.II-641-II-644. [2] Benini L. and G. De Micheli, “State Assignment for Lower Power Dissipation”, IEEE Journal of Solid State Circuits, vol. 30, no 3, 1995, pp. 258-268.

7. Verilog code States must be explicitly specified by the user. This can be done by explicitly using the bit pattern (e.g., 3’b101), or by defining a parameter (e.g., parameter s3 3’b101) and using the parameter as the case item.

8. Part of Verilog code

9. Ways to further reduce Power State duplication: Switching activity reduced from 1.27 to 1.17

10. Duplicate Fetch (12 states) 0000 (0) 0010 (2) 0100 (4) 0110 (6) 0111 (7) 0101 (5) 0011 (3) 1101 (13) 1011 (11) 0001 (1) sw 1000 (8) 1001 (9) Fetch1 lw, sw lw R B J Decode Exception Fetch2 1 1 1 22 2 1 1 1 1 1 1 1 2 1 1 1

11. 11 states 0000 (0) 0010 (2) 0100 (4) 0110 (6) 0111 (7) 0101 (5) 0011 (3) 1000 (8) 1001 (9) 0001 (1) Fetch lw, sw lw sw R B J Decode 1010 (10) Exception

12. One Hot Encoding E.g. 4 states need 4 flip flops. Only one flop will be active ("hot") in a state. 1000 (8) 0001 (1) 0010 (2) 0100 (4)

13. Advantages Low power (since only one toggle when state changes) Simple decoding logic. (Greatly reduces the complexity of CL) Popular method is onehot. FPGA has lot of registers compared to CPLD. so onehot is more suitable for FPGA

14. Clock gating 0000 (0) 0010 (2) 0100 (4) 0110 (6) 0111 (7) 0101 (5) 0011 (3) 1000 (8) 1001 (9) 0001 (1) Fetch lw, sw lw sw R B J Decode 1010 (10) Exception

15. Clock gating D Q Gating signal clk

16. Binary (optimized)

17. Duplicated

18. Onehot

19. Experiment results (powersim) randomoptimizedonehotState duplicate average dynamic power uw 6.89494.6450 (32.6%) 0.5913 (91.4%) 4.7089 (31.7%) average glitch power uw 6.87114.6303 (32.6%) -0.0053 (??)5.0878 (26%) average leakage power uw 2.31532.27862.29182.3993 Total uw 9.21036.9236 (24.8%) 2.8831 (68.7%) 7.0083 (23.9%) Worst delay 10000 7110000 number of gates 93978298

20. Conclusion

21. Thank You! Questions?