1. Pulse-Width Modulated DAC
Lecture 11.3
Verilog
Section 11.5

2. 8-Bit Counter

3. Pulse-Width Modulation

4. module counter8 ( Q ,clr ,clk );
input clr ;
wire clr ;
input clk ;
wire clk ;
output [7:0] Q ;
reg [7:0] Q ;
// 8-bit counter
clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q <= Q + 1;
end
endmodule

5. module PWM(clk,clr,duty,pwm);
input clk, clr;
input [7:0] duty;
output pwm;
reg pwm;
wire [7:0] count;
wire set, reset;
assign set = &count;
assign reset = (count == duty);
set or posedge reset or posedge clr)
begin
if(clr == 1)
pwm <= 0;
else
if(set == 1)
pwm <= 1;
if(reset == 1)
end
counter8 CNT(.Q(count),.clr(clr),.clk(clk));

6. Simulation of PWM