1. CS 150 – Fall 2005 - Lec #26 – Digital Design – 1 Digital Design and System Implementation zOverview of Physical Implementations zCMOS devices zCMOS transistor circuit functional behavior yBasic logic gates yTransmission gates yTri-state buffers yFlip-flops vs. latches revisited

2. CS 150 – Fall 2005 - Lec #26 – Digital Design – 2 The stuff out of which we make systems Overview of Physical Implementations zIntegrated Circuits (ICs) yCombinational logic circuits, memory elements, analog interfaces zPrinted Circuits (PC) boards ysubstrate for ICs and interconnection, distribution of CLK, Vdd, and GND signals, heat dissipation zPower Supplies yConverts line AC voltage to regulated DC low voltage levels zChassis (rack, card case,...) yholds boards, power supply, fans, provides physical interface to user or other systems zConnectors and Cables

3. CS 150 – Fall 2005 - Lec #26 – Digital Design – 3 Integrated Circuits z Primarily Crystalline Silicon z 1mm - 25mm on a side z 100 - 200M transistors z (25 - 50M “logic gates") z 3 - 10 conductive layers z 2005 - feature size ~ 90nm = 0.09 x 10 -6 m z “CMOS” most common - complementary metal oxide semiconductor zPackage provides: yspreading of chip-level signal paths to board-level yheat dissipation. zCeramic or plastic with gold wires Chip in Package

4. CS 150 – Fall 2005 - Lec #26 – Digital Design – 4 Multichip Modules (MCMs) zMultiple chips directly connected to a substrate (silicon, ceramic, plastic, fiberglass) without chip packages Printed Circuit Boards zfiberglass or ceramic z1-25 conductive layers z1-20in on a side zIC packages are soldered down

5. CS 150 – Fall 2005 - Lec #26 – Digital Design – 5 Integrated Circuits zMoore’s Law has fueled innovation for the last 3 decades z“Number of transistors on a die doubles every 18 months.” zWhat are the consequences of Moore’s law?

6. CS 150 – Fall 2005 - Lec #26 – Digital Design – 6 Integrated Circuits zUses for digital IC technology today: yStandard microprocessors xUsed in desktop PCs, and embedded applications (ex: automotive) xSimple system design (mostly software development) yMemory chips (DRAM, SRAM) yApplication specific ICs (ASICs) xcustom designed to match particular application xcan be optimized for low-power, low-cost, high-performance xhigh-design cost / relatively low manufacturing cost yField programmable logic devices (FPGAs, CPLDs) xcustomized to particular application after fabrication xshort time to market xrelatively high part cost yStandardized low-density components xstill manufactured for compatibility with older system designs

7. CS 150 – Fall 2005 - Lec #26 – Digital Design – 7 CMOS Devices Cross Section The gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation, the device acts like a switch. Top View zMOSFET (Metal Oxide Semiconductor Field Effect Transistor) nFET pFET

8. CS 150 – Fall 2005 - Lec #26 – Digital Design – 8 Transistor-level Logic Circuits zInverter (NOT gate): z NAND gate z Note: yout = 0 iff both a AND b = 1 therefore out = (ab)’ ypFET network and nFET network are duals of one another. How about AND gate?

9. CS 150 – Fall 2005 - Lec #26 – Digital Design – 9 Transistor-level Logic Circuits znFET is used only to pass logic zero zpFet is used only to pass logic one zFor example, NAND gate: Simple rule for wiring up MOSFETs: Note: This rule is sometimes violated by expert designers under special conditions

10. CS 150 – Fall 2005 - Lec #26 – Digital Design – 10 Transistor-level Logic Circuits zNAND gate Other more complex functions are possible. Ex: out = (a+bc)’ z NOR gate z Note: yout = 0 iff both a OR b = 1 therefore out = (a+b)’ yAgain pFET network and nFET network are duals of one another

11. CS 150 – Fall 2005 - Lec #26 – Digital Design – 11 zTransmission gates are the way to build “switches” in CMOS zIn general, both transistor types are needed: ynFET to pass zeros ypFET to pass ones zThe transmission gate is bi-directional (unlike logic gates) zDoes not directly connect to Vdd and GND, but can be combined with logic gates or buffers to simplify many logic structures Transmission Gate

12. CS 150 – Fall 2005 - Lec #26 – Digital Design – 12 Pass-Transistor Multiplexer z2-to-1 multiplexer: c = sa + s’b zSwitches simplify the implementation: s s’ b a c

13. CS 150 – Fall 2005 - Lec #26 – Digital Design – 13 4-to-1 Pass-transistor Mux zThe series connection of pass-transistors in each branch effectively forms the AND of s1 and s0 (or their complement) z20 transistors

14. CS 150 – Fall 2005 - Lec #26 – Digital Design – 14 Alternative 4-to-1 Multiplexer zThis version has less delay from in to out zCare must be taken to avoid turning on multiple paths simultaneously (shorting together the inputs) 36 Transistors

15. CS 150 – Fall 2005 - Lec #26 – Digital Design – 15 Tri-state Buffers z Transistor circuit for inverting tri-state buffer: “high impedance” (output disconnected) zVariations Tri-state Buffer: “transmission gate” Inverting buffer Inverted enable

16. CS 150 – Fall 2005 - Lec #26 – Digital Design – 16 Tri-state Buffers zBidirectional connections: z Busses: Tri-state buffers are used when multiple circuits all connect to a common bus. Only one circuit at a time is allowed to drive the bus. All others “disconnect”.

17. CS 150 – Fall 2005 - Lec #26 – Digital Design – 17 Tri-state Based Multiplexer zMultiplexer If s=1 then c=a else c=b z Transistor Circuit for inverting multiplexer:

18. CS 150 – Fall 2005 - Lec #26 – Digital Design – 18 D-type Edge-triggered Flip-flop zThe edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering) yAt all other times the output Q is independent of the input D (just stores previously sampled value) yThe input must be stable for a short time before the clock edge.

19. CS 150 – Fall 2005 - Lec #26 – Digital Design – 19 Transistor-level Logic Circuits Positive Level-sensitive latch: Latch Transistor Level: clk’ clk clk’ Positive Edge-triggered flip- flop built from two level- sensitive latches:

20. CS 150 – Fall 2005 - Lec #26 – Digital Design – 20 State Machines in CMOS zTwo Phase Non-Overlapping Clocking Combinational Logic REGREG REGREG In Out State P1 P2 CLK P1 P2 1/2 Register