1. Redundant Logical AND using Artificial Neural Networks
A “mini” research project done for an artificial intelligence course at the University of Portland, Fall ‘03
By: Dan Gebhardt

2. DISCLAIMER!!
This research is VERY PRELIMINARY, and done over a very short period.
You will probably be able to take apart, or even squash, the experiment…There are many “holes”!
Example: why didn’t I choose a more interesting gate to study, like NAND? I don’t know… ;-)

3. Motivation and Goals
Most circuits may stop functioning correctly if a single transistor fails.
Space-based electronics need much shielding to protect against radiation.
Redundancy at a gate level may offer some advantages in this area.
ANNs may provide a way to do this – they are less susceptible to total failure at the loss of a small portion of their neurons.

4. Intro to Neural Networks
ANNs built of neurons.
Neurons can be connected in a variety of ways and trained to perform functions including:
Pattern recognition
Control systems
Approximating mathematical functions

5. Neuron Model

6. Basic ANN – the Perceptron
Input layer
Hidden layer

7. Experiment Description
Use a perceptron ANN trained as an AND logic gate.
Try three architecture variations: (1x4, 1x8, 2x4 -- hidden layers, neurons/layer).
“Destroy” a neuron by setting its output to 0.
Measure redundancy by comparing output of “damaged” ANN to ideal output of TTL logic levels (0:0-.4V, 1:2.4-5V) scaled to a range of 0-1.
ANN simulator: JOONE (Java Object Oriented Neural Engine)

8. Example: 1x4

9. Results
Mixed – some destroyed neurons changed output little, others significantly.
The 1x8 network seemed to have the best redundancy, followed by the 2x4 and 1x4.
Metric of performance is “Percent of Ideal” for each test case.
100% ideal = 0 output for “low”; 1 output for “high”.
0% ideal = .08 output for “low; .48 output for “high”

10. Results (1x4)

11. Results (1x8)

12. Results (2x4)

13. Results (2x4) cont.

14. Conclusion
There is potential to create robust logic gates from an ANN.
More experimentation needed to determine the performance for varying networks, input values, and logic gates.
Hardware implementation needs to be taken into account.
A potential application: reducing necessary shielding in space-based systems.