1. The Design Process Outline Goal Reading Design Domain Design Flow
Behavioral Design
Structural Design
Physical Design
Management of Complexity
Goal
Understand phases of design process
Understand complexity management
Understand where tools are needed
Reading
Ch. 1-4, Practical Programming in Tcl and Tk

2. Design Domain Behavioral Domain Structural Domain App PMS OS CPU Prog
Proc
RTL
Inst
Gate
Xistor
Process
Field
Circuit
Xistor
Logic
Cell
Architecture
Module
Board
Box
Physical
Domain

3. Design Flow Feedback Design Specification Verify Function Behavioral
Sim., DRC
Verify Function
Mapping
Design
Styles
Structural
Design
Sim., DRC
Verification
Function
Speed, Power
Mapping
Physical
Design
Technology
Simulation
Design Rule Checking
Manuf.
Data
Manufacturing
Specification

4. Design Phase Upper Design Level Map to more detailed Synthesis
design representation.
Usually just
rework design
Determine if design meets
performance objectives,
obeys manufacturing rules.
Often contained as part of synthesis tool inner loop.
Analysis
Reject
Might require
starting over
Determine if equivalent to more abstract design. Human error or tool bug if not.
Verification
Validation
Reject
Lower Design Level

5. Behavioral Design Map design spec to formal behavioral description
design spec == user desires
“a cheap 100MHz Pentium chip”
often not formally described
design and behavioral spec often developed together
Approach
use behavioral hardware description language (HDL)
Verilog
VHDL
HDL is programming language superset
support for timing, modules
verify HDL implements design spec
usually through simulation
check that HDL is self-consistent
“compile” and simulate

6. Structural Design Map behavioral spec to structural spec Approach +
c = a + b
Map behavioral spec to structural spec
partition into functional blocks - the netlist
targets for eventual physical design
Approach
use behavioral modules as starting point
decompose each block to finer detail
function to gates to transistors, etc.
stop at manufacturing interface
logic design - boolean equations => gates
simulation to verify structure has correct behavior
interconnect verification
design rule checking
feedback from physical design - back annotation
for performance verification
RegA
RegB +
RegC
No!

7. Physical Design Map from structure to physical implementation Approach
target technology
technology mapping
netlist to 2-D layout
Approach
partition into boards, modules, chips, cells, layout
place and route
fix cell locations
route wiring
cell layout
design rule checking
circuit extraction
interconnect verification
back annotation

8. Management of Complexity
Bigger, faster designs have more coupling in design flow
more feedback => more design iterations => higher cost
simultaneous design => complex tools
cannot do “technology independent” design
Typical big design
10M transistors
300 MHz clock rate
beyond brute force approaches
Solutions
hierarchy
regularity
abstraction
simplification

9. Hierarchy Structure design as you would a program “procedure calls”
stop at manufacturing interface - “atoms” of IC universe
ALU
Shift
Reg
Mult µP
Datapath
Cache
I/O
1-Bit ALU
SRAM
Use ALU cell
from library •
Design SRAM
cell by hand •

10. Regularity Use replication Examples Enhancement
behavioral - call same procedure many times
structural - instantiate same cell many times
physical - instantiate same cell many times
Examples
bit in SRAM array
bit slice in datapath
Enhancement
module generators
procedure call for structural and physical design
pitch matching
array logic
PLA, ROM

11. Abstraction Use most abstract representation possible
hide information => less memory
simpler representation => less CPU time
to generate
to analyze!
Generate information only as needed
cost too high to generate and discard
Accuracy-cost tradeoff
never enough resources
for full verification
performance prediction
optimization

12. Simplification Restrict design space Restrict object types
restrict technology
only single-poly, double-metal CMOS
restrict circuit family
only digital
only complementary gates
restrict design style
only gate array
Restrict object types
only rectangular mask geometry
no overlapping layout cells

13. Implications for EDA Tool Design
Support the design flow
but tools also determine the design flow
Limit domain
but entire application range must be covered
Restrict representations
a tool box, not a Swiss Army knife
Bridge domains
verification - e.g. logic vs. layout
concurrent design
Bridge representations
verification - e.g. netlist vs. geometry
sufficient accuracy with acceptable speed
EDA tools must meet designer’s needs