Download presentation
Presentation is loading. Please wait.
1
Latches Module M10.1 Section 7.1
2
Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only on current input but also on past input values –Need some type of memory to remember the past input values
3
Cross-coupled Inverters State 1 State 2
4
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand
5
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand
6
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand
7
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set
8
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store
9
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store
10
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store
11
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 0 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset
12
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset
13
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0
14
!S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0
15
S-R Latch !S !R Q !Q S R CLK S R CLK !S !R Q !Q 0 0 1 1 1 Q 0 !Q 0 Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q 0 !Q 0 Store
16
D Latch Q !Q CLK D !S !R S R S R CLK Q !Q 0 0 1 Q 0 !Q 0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 !Q 0 Store 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q
17
D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.
18
D Latch CLK D Q E x y z x y z Does NOT latch z = z $ x = 0 $ 1 = 1 Latches on following edge of clock
19
D Latch CLK D Q E x y z x y z Does latch z = z $ x = 0 $ 1 = 1 Use narrow pulse If x remains high, successive clock pulses will toggle z
Similar presentations
© 2024 SlidePlayer.com. Inc.
All rights reserved.