1. CMOL vs NASICs T. Wang University of Massachusetts, Amherst September 29, 2005

2. Teng Wang@Umass2 Agenda Problems of pure nanoelectronics Problems of Nano-CMOS interface Advantages Problems Conclusions on CMOL

3. Teng Wang@Umass3 Why not Pure Nanoelectronics? Problems of Nanodevices  Simple devices: Limited functionality  Complex devices: Vulnerable to temperature  Voltage gain<1, signal attenuation Hybrid Architecture  Nanodevices + CMOS circuits  Interface between CMOS and nanodevices

4. Teng Wang@Umass4 My Points FET has the ability to restore signals Our NASICs are also hybrid

5. Teng Wang@Umass5 CMOS/Nano Interface Stochastic assembling:  Limited connectivity Long time to program  Resistance of interface affects performance  Fabrication issue

6. Teng Wang@Umass6 CMOS/Nano Interface in CMOL The key idea is to tilt nanoarray at a certain angle α Each nanowire can fall on a certain CMOS pin (for addressing)

7. Teng Wang@Umass7 My Points sin(a)=F nano /F CMOS cos(a)=n* F nano /F CMOS (F nano /F CMOS ) 2 + (n* F nano /F CMOS ) 2 =1 (F nano /F CMOS ) 2 =n 2 +1 F nano /F CMOS can not be arbitrary. a must be precisely controlled. Maybe it can reduce the overhead of CMOS

8. Teng Wang@Umass8 CMOL Memory Nanodevices for memory cell CMOS for coding, decoding, sensing, I/O Fault tolerance:  Reconfiguration  Hamming codes

9. Teng Wang@Umass9 My Points Reconfiguration is an extra assumption. How to decide the size of block?

10. Teng Wang@Umass10 Area Efficiency of CMOL Memory CMOL memory is denser than CMOS memory Reconfiguration improves fault- tolerance High yield of single bit is still required. The area per useful bit as a function of single bit yield, for hybrid and purely memories.

11. Teng Wang@Umass11 My Points The threshhold of acceptable single-bit yield is too high for current nanotechnology What’s the yield of total chip?

12. Teng Wang@Umass12 CMOL Logic Circuits LUT based FPGA: address decoding and sensing require CMOS circuits. For small LUT, CMOS overhead is great. PLA based FPGA:  The same problem as LUT-based FPGA  Power dissipation (10KW/cm 2 ) CMOL FPGA: reconfigurable regular structure

13. Teng Wang@Umass13 My Points Why power is so huge? Most research indicates that nanodevices consume extremely low power: <10W/cm 2

14. Teng Wang@Umass14 CMOL FPGA – A Single Cell Logics in CMOS Interconnections in Nanowires

15. Teng Wang@Umass15 My Points Density advantage? Logics in CMOS not nano How to connect the red/blue terminals with nanowires?

16. Teng Wang@Umass16 CMOL FPGA – A NOR Gate Wire-OR logic on nanowires? NOR is enough for arbitrary logic functions

17. Teng Wang@Umass17 My Points Does nanowire have wire-OR/AND property? 3 CMOS inverter -> a NOR gate? It seems even worse than CMOS.

18. Teng Wang@Umass18 CMOL CrossNets: Neuromorphic Network CrossNet is an architecture of neuromorphic network  Somas (in CMOS): Neural cell bodies  Axons and dendrites (mutually perpendicular nanowires)  Synapses (switches between nanowires): control coupling between axons and dendrites

19. Teng Wang@Umass19 Schematic of CrossNet Light-gray squares in panel (a) show the somatic cells as a whole. Signs show the somatic amplier input polarities. Green circles denote nanodevices forming elementary synapses.

20. Teng Wang@Umass20 Conclusions CMOL for:  Memories: reconfiguration, overhead of CMOS  FPGAs: really denser than CMOS?  Neuromophic networks: no comments Density, delay, power dissipation  Delay should be better than NASIC, since it use a new layer for CMOS.  Power dissipation is hard to compare with NASIC.

21. Teng Wang@Umass21 Contact us Email: twang@ecs.umass.edu Thank you!