Presentation is loading. Please wait.

Presentation is loading. Please wait.

Integration and Automation KEY to Productivity Boost in Analog and Mixed Signal Designs Sarah Xu Managing Director of China Operations Magma Design Automation,

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Integration and Automation KEY to Productivity Boost in Analog and Mixed Signal Designs Sarah Xu Managing Director of China Operations Magma Design Automation,"— Presentation transcript:

1 Integration and Automation KEY to Productivity Boost in Analog and Mixed Signal Designs Sarah Xu Managing Director of China Operations Magma Design Automation, Inc.

2 June 11, 2015 - Magma Confidential - 2 World is Mixed Signal…And IntegratedWorld is Mixed Signal Create Watch Talk Capture Listen

3 June 11, 2015 - Magma Confidential - 3 Mixed Signal = Digital + Analog/Custom The International Technology Roadmap for Semiconductors (ITRS) The cutting edge of DIGITAL design is 45nm. Active tape outs have been done. The bleeding edge of ANALOG design is 90nm, and many are trapped at 130 and 250nm (5 to 10 year old technology!)

4 June 11, 2015 - Magma Confidential - 4 Outline The Evolution of Digital Tools The Evolution of Analog Tools The Requirements for Analog Automation Mixed Signal Considerations Magma 2.0 – Titan

5 June 11, 2015 - Magma Confidential - 5 Outline The Evolution of Digital Tools The Evolution of Analog Tools The Requirements for Analog Automation Mixed Signal Considerations Magma 2.0 – Titan

6 June 11, 2015 - Magma Confidential - 6 Evolution of Digital Tools 1960s 1970s 1980s Capture design by hand crafting Functional and timing verification by visual inspection Implementation by hand drawing Capture design by gate level schematics Functional verification through event driven logic simulation Timing verification by STA Capture design by RTL Automated logic synthesis Automated place and route

7 June 11, 2015 - Magma Confidential - 7 Outline The Evolution of Digital Tools The Evolution of Analog Tools The Requirements for Analog Automation Mixed Signal Considerations Magma 2.0 – Titan

8 June 11, 2015 - Magma Confidential - 8 Evolution of Analog Tools 1960s 1970s 1990s Capture design by hand crafting Functional and timing verification through visual inspection Implementation by hand drawing Capture design by gate level schematics Functional verification through event driven logic simulation Timing verification by STA Capture design by RTL Automated logic synthesis Automated place and route Capture design by hand crafting Functional and timing verification through test bench in real world setting Analog simulation via SPICE Capture design by transistor level schematics

9 June 11, 2015 - Magma Confidential - 9 Limitation of Today’s Analog Tools Most of today's analog tools were conceived in 1990s The underlying architectures were never intended to support the sophisticated demands of a mixed-signal design environment Today's analog design and verification tools are essentially limited to transistor-level schematics Very limited success w.r.t. automation Representing analog functionality at a high-level of abstraction and then using these representations to generate transistor-level equivalents Automatically optimizing analog circuits Automatically placing-and-routing analog circuits

10 June 11, 2015 - Magma Confidential - 10 Synthesis, Place & Route Turnaround Time 2 Days Digital Design is Automated, Reusable always @ (posedge sm_clock) begin if (reset == 1'b1) current_state <= 2'b00; else current_state <= next_state; end always @ (current_state or sm_in) begin // default values sm_out = 1'b1; next_state = current_state; case (current_state) idle: sm_out = 1'b0; if (sm_in) next_state = 2'b11; write: sm_out = 1'b0; if (sm_in == 1'b0) next_state = 2'b10; read: if (sm_in == 1'b1) next_state = 2'b01; wait: if (sm_in == 1'b1) next_state = 2'b00; endcase end endmodule RTL ADC PLL SERDES Memory Synthesized Digital Logic Custom Digital Cells Digital

11 June 11, 2015 - Magma Confidential - 11 Synthesis, Place & Route Turnaround Time 2 Days Analog / Custom Design is NOT Automated, NOT Reusable DigitalAnalog IP Process Migration Turnaround Time 6-12 Months Integration Turnaround Time 4-8 Weeks Transcievers, SERDES… Turnaround Time 3-6 Months ADC PLL SERDES Memory Synthesized Digital Logic Custom Digital Cells

12 June 11, 2015 - Magma Confidential - 12 Why? For every new process node, designs have to be re-created by-hand from scratch Analog/Custom Design System Design Excel, C, Paper, Verilog A/AMS Excel, C, Paper, Verilog A/AMS C, Matlab, Spice Circuit Design Excel, Matlab, Paper… Schematic Capture, Spice Schematic Capture, Spice Physical Design Placement, Routing, Extraction, Spice Manual Design & Constraints It’s a Very Hard Problem To Solve! Accuracy ? Automation ? Re-use ? Ease of Use ? Compatibility ?

13 June 11, 2015 - Magma Confidential - 13 Mixed Signal = Digital + Analog/Custom The International Technology Roadmap for Semiconductors (ITRS) The cutting edge of DIGITAL design is 45nm. Active tape outs have been done. The bleeding edge of ANALOG design is 90nm, and many are trapped at 130 and 250nm (5 to 10 year old technology!)

14 June 11, 2015 - Magma Confidential - 14 Outline The Evolution of Digital Tools The Evolution of Analog Tools The Requirements for Analog Automation Mixed Signal Considerations Magma 2.0 – Titan

15 June 11, 2015 - Magma Confidential - 15 Wish List for Next Generation Analog Tools The ability to specify an analog function at a high level of abstraction and to then automatically translate this representation into its transistor-level equivalent The ability to automatically perform analog refinement and optimization The ability to automatically place analog components on the IC The ability to automatically route analog components on the IC The capability to automate the migration process for an analog design from one process/technology node to another and from one foundry to another

16 June 11, 2015 - Magma Confidential - 16 Outline The Evolution of Digital Tools The Evolution of Analog Tools The Requirements for Analog Automation Mixed Signal Considerations Magma 2.0 – Titan

17 June 11, 2015 - Magma Confidential - 17 Wish List for Next Generation Mixed Signal Tools Analog and digital design and verification engines should employ a unified database The environment must provide extreme capacity and performance Such as loading the entire full-chip database in a minute or less and re-drawing all of the analog and digital layers in seconds The environment must support extremely accurate parasitic extraction and full-chip mixed-signal simulation and analysis At the chip-finishing stage, the environment must support automatic global routing

18 June 11, 2015 - Magma Confidential - 18 Outline The Evolution of Digital Tools The Evolution of Analog Tools The Requirements for Analog Automation Mixed Signal Considerations Magma 2.0 – Titan

19 June 11, 2015 - Magma Confidential - 19 United Custom And Digital Database Full Chip Timing / Signal Noise Analysis Integrated Full Chip LVS, DRC and Extraction Magma 2.0: Mixed-Signal Design Titan : Mixed-Signal Platform Digital & Analog Integration Mixed Signal Physical Constraints * Shape Based, Constraint Driven Routing Schematic Editor Layout Editor Analog IP Process Migration * Integrated Simulation Environment Including Waveform Editor * Beta / Limited production now Full Production Q3-08

20 June 11, 2015 - Magma Confidential - 20 Driving the Shift to Titan Accuracy Production proven FineSim integrated simulation environment Automation Analog IP process migration automation Integration  Ease of Use Integration to support digital, custom, analog flows seamlessly Integration with FineSim, Talus, Quartz DRC/LVS Faster time to tapeout Up to 10x speed and capacity advantage over old solutions Speed and capacity to iterate quickly and close Smooth Migration Path OpenAccess Compatibility Easily transition existing design to Titan

21 June 11, 2015 - Magma Confidential - 21 Titan : The Only Mixed-Signal Platform Embedded Talus

22 June 11, 2015 - Magma Confidential - 22 Titan : High Speed, High Capacity Layout & Schematic Editor Responsive all-layer redraw, pan & zoom Integrated GUI with menus, hotkeys & tear-off panels Fully scriptable Tcl/Tk interface Cell hierarchy browser Edit-in-place correct across hierarchy Full cross-probing: schematics, DRC errors & parasitics Example: Layout Editing of 42GB GDSII Design Full Chip Open  4 min Redraw  8 sec Zoom In by 2  4 sec Pan time to random points  7 sec

23 June 11, 2015 - Magma Confidential - 23 Titan Accuracy Integrated Analog Simulation Environment FineSim SPICE : Fastest Spice Simulator Unified Single Executable Simulator Native-Parallel™ Technology (NPT) FineSim SPICE (Full SPICE with NPT) Increased analog SPICE capacity Single-CPU FineSim SPICE 3-10X Faster Than Other SPICE Engines FineSim Pro (Fast SPICE with NPT) 1-3% SPICE Accuracy FineSim Customer Success Toshiba, Maxim, Faraday, AMD, SiliconBlue, STARC, Sigma Design...

24 June 11, 2015 - Magma Confidential - 24 Fully Integrated Custom/Digital Analysis Sign-off Quality Analysis DRC, LVS Extraction, Timing Noise, Power DFM, Yield Complete Integration Push-button “invocation” Cross-probing debug Fast incremental iteration

25 June 11, 2015 - Magma Confidential - 25 Magma’s Unified Routing System Unified, Shape-Based Custom & Chip Finishing Router Shape-based flexibility Built for modern nm geometries and design sizes Supports Schematic driven Layout Custom routing constraints Automates critical signal handling Net length control (min, max, match T-line) Signal shielding (parallel, tandem, coax) Differential pair support Analog-digital global routing Ensures timing consistency across digital and custom routing regions Speed and capacity to easily handle the largest mixed-signal chips Timing-Driven Global Router Talus Digital Router Titan Custom Shape Router

26 June 11, 2015 - Magma Confidential - 26 Titan: Open Architecture OA PCells™ / PyCells™ OA GDS SPICE Verilog LEF / DEF Volcano Live Link Live Link GDS 3 rd Party Tools 3 rd Party Tools PDK

27 June 11, 2015 - Magma Confidential - 27 Analog IP Design & Process Migration Original Design Time Process Migration Time Circuit Design80 days50 days Layout60 days IP process migration requires almost as much circuit design and layout time as the original rev! *Source: Rambus, www.scdsource.com/article.php?id=39www.scdsource.com/article.php?id=39

28 June 11, 2015 - Magma Confidential - 28 Modern Approach to Analog IP Process Migration Write a specification on a computer Analyze the resulting circuit “Implement and Optimize” it Re-Use it Change specifications Change process nodes Do in minutes what would take days and months “the old way” Design & Foundry Specific Library Analog IP Process Migration Design Constraints Schematic & Layout Constraints

29 June 11, 2015 - Magma Confidential - 29 Sabio Technology Schematic / Layout Editor Mixed Signal Physical Constraints Integrated Simulation (FineSim) Revolutionary Analog IP Design & Process Migration AnalogWare Matlab Specs Standard Custom Sized and Verified Design Process Compiler Process Models PDK Titan Analog Optimization (Circuit & Physical) Titan Analog Optimization (Circuit & Physical) Titan

30 June 11, 2015 - Magma Confidential - 30 Titan: Process Migration Results Order Of Magnitude Faster Porting While Achieving Equal Or Better Performance Without Titan AOWith Titan AO PCI-E IO driver, 2.5GHz (17 corners) 2 weeks1 hour Bandgap (33 corners) 3 weeks5 min 6.4GHz SERDES Linear Equalizer (9 corners) 2 weeks5 min 1.5GHz, 1V PLL (9 corners) 2 months1 hour 12 bit pipeline, 100MS, system + op-amps (5 corners) 2 weeks1 hour

31 June 11, 2015 - Magma Confidential - 31 Mixed-Signal Platform Embedded Talus Shape-Based Routing Mixed-Signal Verification Analog Block Design & Migration Speed and Capacity Compatibility Accommodate legacy data OA Compatible Titan: Integrated Mixed-Signal Platform ++ Mixed-Signal Design

32 June 11, 2015 - Magma Confidential - 32

Download ppt "Integration and Automation KEY to Productivity Boost in Analog and Mixed Signal Designs Sarah Xu Managing Director of China Operations Magma Design Automation,"

Similar presentations

TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.

TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.
1 General-Purpose Languages, High-Level Synthesis John Sanguinetti High-Level Modeling.

1 General-Purpose Languages, High-Level Synthesis John Sanguinetti High-Level Modeling.
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.

ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
1 Cleared for Open Publication July 30, 2004 04-S-2144 P148/MAPLD 2004 Rea MAPLD 148:Is Scaling the Correct Approach for Radiation Hardened Conversions.

1 Cleared for Open Publication July 30, S-2144 P148/MAPLD 2004 Rea MAPLD 148:"Is Scaling the Correct Approach for Radiation Hardened Conversions.
Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown.

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown.
© IMEC 2010 MIXED SIGNAL RADIATION TOLERANT DESIGN WITH DARE KNUT ASIC.

© IMEC 2010 MIXED SIGNAL RADIATION TOLERANT DESIGN WITH DARE KNUT ASIC.
© 2015 Synopsys, Inc. All rights reserved.1 Timing Analysis in a Mixed Signal World TAU Workshop Panel Session Jim Sproch March 12, 2015.

© 2015 Synopsys, Inc. All rights reserved.1 Timing Analysis in a Mixed Signal World TAU Workshop Panel Session Jim Sproch March 12, 2015.
Ch.3 Overview of Standard Cell Design

Ch.3 Overview of Standard Cell Design
Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.

Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.
Lecture 1 Design Hierarchy Chapter 1. Digital System Design Flow 1.Register-Transfer Levl (RTL) – e.g. VHDL/Verilog 2.Gate Level Design 3.Circuit Level.

Lecture 1 Design Hierarchy Chapter 1. Digital System Design Flow 1.Register-Transfer Levl (RTL) – e.g. VHDL/Verilog 2.Gate Level Design 3.Circuit Level.
MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.

MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.
The Design Process Outline Goal Reading Design Domain Design Flow

The Design Process Outline Goal Reading Design Domain Design Flow
Tejas Bhatt and Dennis McCain Hardware Prototype Group, NRC/Dallas Matlab as a Development Environment for FPGA Design Tejas Bhatt June 16, 2005.

Tejas Bhatt and Dennis McCain Hardware Prototype Group, NRC/Dallas Matlab as a Development Environment for FPGA Design Tejas Bhatt June 16, 2005.
ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction.

ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction.
ECE 699: Lecture 2 ZYNQ Design Flow.

ECE 699: Lecture 2 ZYNQ Design Flow.
ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction.

ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction.
Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,

Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,
EDA TOOLS. Why EDA? Imagine a Intel based micro processor having 1.5 million transistors. Would it be feasible to design such a complex system with help.

EDA TOOLS. Why EDA? Imagine a Intel based micro processor having 1.5 million transistors. Would it be feasible to design such a complex system with help.
© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.

© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
Robust Low Power VLSI R obust L ow P ower VLSI Memory Management Units for Instruction and Data Cache for OR1200 CPU Core Arijit Banerjee ASIC/SOC Class.

Robust Low Power VLSI R obust L ow P ower VLSI Memory Management Units for Instruction and Data Cache for OR1200 CPU Core Arijit Banerjee ASIC/SOC Class.

Similar presentations

Ads by Google