1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 24 - Subsystem Design (cont’d) Spring 2005

2. ECE 425 Spring 2005Lecture 24 - Subsystem Design2 Announcements  Reading  Wolf: 6.1-6.9  These notes drawn in part from handouts by  J. Rabaey, Digital Integrated Circuits, © Prentice-Hall 1995.

3. ECE 425 Spring 2005Lecture 24 - Subsystem Design3 Where We Are:  Last Time:  Custom Subsystem Design - Shifters, Adders  Today:  Custom Subsystem Design Continued - Multipliers  DAC Video: “Designing Mega-ASICs in Nanotechnology”

4. ECE 425 Spring 2005Lecture 24 - Subsystem Design4 Subsystem Design  General TechniquesGoals  Pipelining  Datapath Design  Common Subsystems  Shifters  Adders   ALUs  Multipliers  Memories  Structured Logic

5. ECE 425 Spring 2005Lecture 24 - Subsystem Design5 Carry/Skip Adder  Key idea: in some cases, carry out = carry in  Bypass gate - "forward" carry signal  Break forwarding into groups FA skip FA skip FA skip group P i-1 PiPi P i+1

6. ECE 425 Spring 2005Lecture 24 - Subsystem Design6 Carry/Select Adder  Key idea: compute two sum values  sum assuming carry=0,  sum assuming carry=1  Select proper result based on carry in

7. ECE 425 Spring 2005Lecture 24 - Subsystem Design7 Manchester Carry Chain  Goal: speed up carry using circuit design  Key idea: use dynamic logic  Conditionally discharge using generate signal  Connect successive bits using propagate signal  worst case discharge path through entire chain Ci’Ci’C i-1 ’

8. ECE 425 Spring 2005Lecture 24 - Subsystem Design8 Serial Adders  Key idea: add one bit at a time  Shift results in/out of adder  Organization: Fig 6-15, p. 328

9. ECE 425 Spring 2005Lecture 24 - Subsystem Design9 Subraction  A-B = A + (-B)  Recall two's complement arithmetic  -B = TC(B) = OC(B) + 1  Get OC(B) with inverter  Use carry in to get +1

10. ECE 425 Spring 2005Lecture 24 - Subsystem Design10 Logical operations  Simple operations: use basic gates  Multiple operations: use 4-1 mux as logic "function block"  Organization: Fig 6-17, p. 330

11. ECE 425 Spring 2005Lecture 24 - Subsystem Design11 Subsystem Design  General TechniquesGoals  Pipelining  Datapath Design  Common Subsystems  Shifters  Adders  ALUs   Multipliers  Memories  Structured Logic

12. ECE 425 Spring 2005Lecture 24 - Subsystem Design12 ALUs  Key idea: compact layout for multiple functions  Build around adder (central component due to carry delay)  Organization: Fig. 6-16, p. 329

13. ECE 425 Spring 2005Lecture 24 - Subsystem Design13 Subsystem Design  General TechniquesGoals  Pipelining  Datapath Design  Common Subsystems  Shifters  Adders  ALUs  Multipliers   Memories  Structured Logic

14. ECE 425 Spring 2005Lecture 24 - Subsystem Design14 Review - Multiplication  Basic algorithm analogous to decimal multiplication  Break multiplier into digits  Multiply one digit at a time; shift multiplicand to form partial products  Create product as sum of partial products  n bit multiplicand X m bit multiplier = (n+m) bit product Multiplicand 0110 (6) Multiplier X 0011 (3) 0110 0000 Product 00010010 (18) Partial Products

15. ECE 425 Spring 2005Lecture 24 - Subsystem Design15 Review - Shift & Add Multiplier  Key idea: store multiplier and product in same register!  As multiplier shifts out….  Product shifts in Multiplicand (32 bits) Product (64 bits) Write Control 32-bit ALU LSB Shift Right LHPROD (32 bits) MP/RHPROD (32 bits) 33 32

16. ECE 425 Spring 2005Lecture 24 - Subsystem Design16 Review - Shift & Add Control START DONE 1. Test PROD0 1a. Add MCND to left half of PROD Place result in left half of PROD 2. Shift PROD right 1 bit 0. LOAD MPY in right half of PROD 32nd Repitition? Product0=1Product0=0 No: <32 Repititions Yes: 32 Repititions

17. ECE 425 Spring 2005Lecture 24 - Subsystem Design17 Review - Booth’s Algorithm  Originally proposed to reduce addition steps  Bonus: works for two’s complement numbers  Uses shifting, addition, and subtraction

18. ECE 425 Spring 2005Lecture 24 - Subsystem Design18 Booth’s Algorithm  Observation: if we can both add and subtract, there are multiple ways to create a product  Example: multiply 2 ten by 6 ten (0010 two X 0110 two )  Product = (2 X 2) + (2 X 4) OR  Product = (2 X -2) + (2 X 8) 0010 X 0110 + 0000 shift + 0010 shift + add + 0000 shift 00001100 0010 X 0110 0000 shift - 0010 shift + subtract 0000 shift + 0010 shift + add 00001100 Regular Algorithm Booth’s Algorithm

19. ECE 425 Spring 2005Lecture 24 - Subsystem Design19 Booth’s Algorithm Continued  Question:  How do we know when to subtract?  When do we know when to add?  Answer: look for “runs of 1s” in multiplier  Example: 001110011  Working from Right to Left, any “run of 1’s” is equal to: - value of first digit that’s one +value of first digit that’s zero  Example : 001110011 First run: -1 + 4 = 3 Second run: -16 + 128 = 112 Total: 112 + 3 = 115

20. ECE 425 Spring 2005Lecture 24 - Subsystem Design20 Implementing Booth’s Algorithm  Scan multiplier bits from right to left  Recognize the beginning and in of a run looking at only 2 bits at a time  “Current” bit a i  Bit to right of “current” bit a i-1 0110011100 Beginning Of Run Middle Of Run End Of Run Bit a i Bit a i-1 Explanation 10Begin Run of 1’s 11Middle of Run of 1’s 01End of Run 00Middle of Run of 0’s

21. ECE 425 Spring 2005Lecture 24 - Subsystem Design21 Implementing Booth’s Algorithm  Key idea: test 2 bits of multiplier at once  10 - subtract (beginning of run of 1’s)  01 - add (end of run of 1’s)  00, 11 - do nothing (middle of run of 0’s or 1’s) Multiplicand (32 bits) Product (64 bits) Write Control 32-bit ALU Shift Left ADD/ SUB 2 Bits 1:0 LHPROD (32 bits) MP/RHPROD (32 bits)

22. ECE 425 Spring 2005Lecture 24 - Subsystem Design22 Subsystem Design: Combinational Multipliers  Key idea: use multiple adders & eliminate registers (or use for pipelining)

23. ECE 425 Spring 2005Lecture 24 - Subsystem Design23 Array Multiplier X3X3 X2X2 X1X1 X0X0 Y0Y0

24. ECE 425 Spring 2005Lecture 24 - Subsystem Design24 Array Multiplier - Critical Paths Critical Path 1 & 2

25. ECE 425 Spring 2005Lecture 24 - Subsystem Design25 Carry-Save Multiplier

26. ECE 425 Spring 2005Lecture 24 - Subsystem Design26 Carry-Save Multiplier - Floorplan

27. ECE 425 Spring 2005Lecture 24 - Subsystem Design27 Wallace-Tree Multiplier

28. ECE 425 Spring 2005Lecture 24 - Subsystem Design28 Other Multiplier Tricks  Use Radix-4 Booth Recoding to reduce number of additions  Sample 3 bits of multiplier and add one of:  - (multiplier * 2)  - (multiplicand * 1) 00  + (multiplicand * 1)  + (multiplicand * 2)  Cited Result that combines these techniques: L. Mori, et. al, “A 10ns 54 X 54 Parallel Structured Full Array Multiplier with 0.5µm Technology”, IEEE Journal of Solid State Circuits, vol. 26, no. 4, April 1991

29. ECE 425 Spring 2005Lecture 24 - Subsystem Design29 Subsystem Design  General TechniquesGoals  Pipelining  Datapath Design  Common Subsystems  Shifters  Adders  ALUs   Multipliers  Memories  Structured Logic