1. 1 Outline Systolic Array Binary Heap Pipelined Heap Hardware Design

2. 2 The Systolic Array Priority Queue Block 1Block 2Block 3Block n Highest value New value NON-INCREASING PRIORITY VALUES Permanent Data Register Temporary Register n = 1000 Hardware required: 1000 comparators, 2000 registers. Performance: constant time.

3. 3 The Binary Heap Priority Queue 14 2357 734 10 1 23 4567 89 1112 16 8 3 1410773324358 123456789 111213 14 VALUE n =1000 Hardware required: 1 comparator, 1 register, 1 SRAM. Performance: O(log n). 15

4. 4 The Pipelined-Heap Modified binary heap data structure Constant-time operation. Similar to the Systolic Array. Good hardware scalability. Similar to the Binary Heap.

5. 5 P-heap Data Structure (B,T)

6. 6 16 245 873 1410 1 23 4567 89 1112131415 enq operation positionvalue 9 1 (a) local-enqueue (1) 16 245 873 1410 1 23 4567 89 1112131415 enq operationpositionvalue 9 2 (b) local-enqueue (2) The Enqueue (Insert) Operation

7. 7 16 245 893 1410 1 23 4567 89 1112131415 enq operationpositionvalue 7 10 (d) local-enqueue (4) 16 245 873 1410 1 23 4567 89 1112131415 enq operation positionvalue 9 5 (c) local-enqueue (3) 16 245 893 1410 23 4567 89 1112131415 1 operation positionvalue 7 (e) Enqueue (contd)

8. 8 245 873 1410 1 23 4567 89 1112131415 (b) local-dequeue (1) deq operationpositionvalue 1 1 16 245 873 1410 23 4567 89 1112131415 (a) operationpositionvalue The Dequeue (Delete) Operation

9. 9 245 8 73 14 10 23 4567 89 1112131415 (d) local-dequeue (3) deq operationpositionvalue 4 245 873 14 10 23 4567 89 1112131415 (c) local-dequeue (2) deq operationpositionvalue 2 2 4 5 8 73 14 10 23 4567 89 1112131415 (e) operationpositionvalue Dequeue (contd) 11 1

10. 10 Pipelined Operation 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 level

11. 11 Hardware Requirements log N SRAMs represent the Binary Array B, N = size of the P-heap. log N registers represent the Token Array T. log N comparators required, one for each level of the P-heap.