1. COE 341: Data & Computer Communications (T081) Dr. Marwan Abu-Amara Chapter 6: Digital Data Communications Techniques

2. COE 341 – Dr. Marwan Abu-Amara 2 Contents 1. Asynchronous and Synchronous Transmission 2. Types of Errors 3. Error Detection a. Parity Check b. Cyclic Redundancy Check (CRC)

3. COE 341 – Dr. Marwan Abu-Amara 3 Asynchronous and Synchronous Transmission: To communicate meaningful data serially between TX and RX, signal timing should be the same at both Timing considerations include:  Rate  Duration  Spacing Need to synchronize RX to TX Two ways to achieve this:  Asynchronous Transmission  Synchronous Transmission RX needs to sample the received data at mid-points So it needs to establish: - Bit arrival time - Bit duration

4. COE 341 – Dr. Marwan Abu-Amara 4 Need for RX and TX Synchronization: Clock drift (example):  If the receiver clock drifts by 1% every sample time,  For T b = 1  sec, total drift after 50 bit intervals = 50 X 0.01 = 0.5  sec  i.e. instead of sampling at the middle, the receiver will sample bit # 50 at the edge of the bit  RX and TX clocks are out-of-synch  Communication Error! In general, # of correctly sampled bits = 0.5 T b /(n/100)T b = 50/n, where n is the % timing error between TX and RX Two approaches for correct reception:  Send only a few bits (e.g. a character) at a time (that RX can sample correctly before losing sync)  Asynchronous Transmission  Keep receiver clock synchronized with the transmitter clock  Synchronous Transmission Transmitter Receiver TX Clock RX Clock TbTb

5. COE 341 – Dr. Marwan Abu-Amara 5 Asynchronous Transmission: Character-Level Synchronization Avoids the timing problem by NOT sending long, uninterrupted streams of bits. So data is transmitted one character at a time:  Has a distinct start bit  Consists of only 5 to 8 bits (so drift will not be a serious problem)  Has a distinct stop bit Character is delimited (at start & end) by known signal elements: start bit – stop element Sync needs to be maintained only for the duration of a character The receiver has a new opportunity to resynchronize at the beginning of next character  Timing errors do not accumulate from character to character

6. COE 341 – Dr. Marwan Abu-Amara 6 Asynchronous Transmission RX “knows” how many bits To expect in a character, and keeps counting them following the ‘start’ bit RX waits for a character following the end of the previous character (Min) The ‘stop’ element confirms end of character  otherwise: Framing Error Stop elements continue (idling) until next character Binary 1 Parity bit: Even or Odd parity? S1: receiver in idling state S2: receive in receiving state S1 S2 Receive Start bit Receive Stop element Receive Stop element

7. COE 341 – Dr. Marwan Abu-Amara 7 Asynchronous Transmission Framing error Erroneous detection of end/start of a character Can be caused by:  Noise: (1 is the idling ‘stop’ bit) 1 1 1 1 0 1 1 1 1 1 …  Incorrect timing of bit sampling due to drift of RX clock affects bit count Erroneous ‘Start’ bit due to noise

8. COE 341 – Dr. Marwan Abu-Amara 8 Asynchronous Transmission Errors due to lack of sync for an 8-bit system Let data rate = baud rate = 10 kbps Bit interval = 1/10k = 100  s Assume RX’s clock is faster than TX by 6% (i.e. RX thinks the bit interval is 94  s) RX checks mid-bit data at 47  s and then at 94  s intervals Bit 8 is wrongly sampled within bit 7 (bit 7 read twice!) Possibility of a framing error at the end 100  s 94  s (Timing for ideal sampling at RX) 47  s Half the bit interval from the ‘start’ rising edge 893

9. COE 341 – Dr. Marwan Abu-Amara 9 Asynchronous Transmission: Efficiency Uses 1 start bit & 2 stop bits: (i.e. 3 non-data bits) with 8-bit characters and no parity:  Efficiency = 8/(8+3) = 72%  Overhead = 3/(8+3) = 28%

10. COE 341 – Dr. Marwan Abu-Amara 10 Asynchronous Transmission – Pros & Cons Advantages: Simple Cheap Good for data with large gaps (keyboard) Cons: Overhead of 2 or 3 bits per character (~20%) Timing errors accumulate for large character sizes

11. COE 341 – Dr. Marwan Abu-Amara 11 Synchronous Transmission: Bit-Level Synchronization Allows transmission of large blocks of data (frames) TX and RX Clocks must be synchronized to prevent timing drift Ways to achieve bit-level sync:  Use a separate clock line between TX and RX Good over short distances Subject to transmission impairments over long distances  Embed clock signal in data e.g. Manchester or Differential Manchester encoding Or carrier frequency for analog signals

12. COE 341 – Dr. Marwan Abu-Amara 12 Synchronous Frame Format Typical Frame Structure Preamble bit pattern: Indicates start of frame Postamble bit pattern: Indicates end of frame Control fields: convey control information between TX and RX Data field: data to be exchanged data field 8-bit flag 8-bit flag control field Preamble/Postamble flags ensure frame-level synchronization

13. COE 341 – Dr. Marwan Abu-Amara 13 Synchronous Transmission: Efficiency Example: HDLC scheme uses a total of 48 bits for control, preamble, and postamble fields per frame: With a data block consisting of 1000 characters (8-bits per character),  Efficiency = 8000/(8000+48) = 99.4%  Overhead = 48/8048 = 0.6% Higher efficiency and lower overhead compared to asynchronous

14. COE 341 – Dr. Marwan Abu-Amara 14 Errors in Digital Transmission Error occurs when a bit is altered between transmission and reception (0  1 or 1  0) Two types of errors:  Single bit errors One bit altered Isolated incidence, adjacent bits not affected Typically caused by white noise  Burst errors Contiguous sequence of B bits in which first, last, and any number of intermediate bits are in error Caused by impulse noise or fading (in wireless) More common, and more difficult to handle Effect is greater at higher data rates What to do about these errors:  Detect them (at least, so we can ask TX to retransmit!)  Correct them (if we can)

15. COE 341 – Dr. Marwan Abu-Amara 15 Error Detection & Correction: Motivation Assume NO error detection or correction: Number of erroneous frames received would be unacceptable Hence, for a frame of F bits, Prob [frame is correct] = (1-BER) F : Decreases with increasing BER & F Prob [frame is erroneous] = 1 - (1-BER) F = Frame Error Rate (FER) 1 0 1 0 1 0 0 0 1 0 1 0 … 0 0 1 1 2 3 4 … … F-2 F-1 F Prob [1 st bit in error] = BER Prob [1 st bit correct] = 1-BER Prob [2 nd bit in error] = BER Prob [2 nd bit correct] = 1-BER Prob [F th bit in error] = BER Prob [F th bit correct] = 1-BER A frame of F bits All bits must be Correct! All bits must be Correct!

16. COE 341 – Dr. Marwan Abu-Amara 16 Motivation for Error Detection & Correction: Example ISDN specifies a BER = 10 -6 for a 64kbps channel Frame size F = 1000 bits What is the FER?  FER = 1 – (1 – BER) F = 1 – (0.999999) 1000 = 10 -3 Assume a continuously used channel How many frames are transmitted in one day Number of frames/day = (64,000/1000) × 24 × 3600 = 5.5296 × 10 6 How many erroneous frames/day?  5.5296 × 10 6 × 10 -3 = 5.5296 × 10 3 Typical requirement: Maximum of 1 erroneous frame /day! i.e. frame error rate is too high!  We definitely need error detection & correction

17. COE 341 – Dr. Marwan Abu-Amara 17 Frame Error Probabilities: P 1 + P 2 + P 3 = 1 Without error detection facility: P 3 = 0, and: P 2 = 1 – P 1 1 0 1 0 1 0 0 0 1 0 1 0 … 0 0 1 Correct Erroneous P1P1 1 - P 1 Errors, Detected Errors, Undetected P3P3 P2P2 With an error detection facility 1000 900 100 80 20

18. COE 341 – Dr. Marwan Abu-Amara 18 Error Detection Techniques Two main error detection techniques:  Parity Check  Cyclic Redundancy Check (CRC) Both techniques use additional bits that are added to the “payload data” by the transmitter for the purpose of error detection

19. COE 341 – Dr. Marwan Abu-Amara 19 Error Detection: Implementation Mismatch: Error Detected

20. COE 341 – Dr. Marwan Abu-Amara 20 Parity Check Simplest error-detection scheme Appending one extra bit:  Even Parity: Will append “1” such that the total number of 1’s is even  Odd Parity: Will append “1” such that the total number of 1’s is odd Example: If an even-parity is used, RX will check if the total number of 1’s is even  If it is not  error occurred Note: even number of bit errors go undetected

21. COE 341 – Dr. Marwan Abu-Amara 21 Cyclic Redundancy Check (CRC) Burst errors will most likely go undetected by a simple parity check scheme Instead, a more elaborate technique called Cyclic Redundancy Check (CRC) is typically implemented CRC appends redundant bits to the frame trailer called Frame Check Sequence (FCS)  FCS is later utilized at RX for error detection In a given frame containing n bits, we define:  k = number of original data bits  (n – k) = number of bits in the FCS field (i.e. additional bits)  So, that the total frame length is k + (n – k) = n bits 1 0 1 0 0 0 1 1 0 1 01110 FCS (n-k) D (k) T(n)

22. COE 341 – Dr. Marwan Abu-Amara 22 CRC Generation CRC generation is all about finding the FCS given the data (D) and a divisor (P) There are three equivalent ways to generate the CRC code:  Modulo-2 Arithmetic Method  Polynomial Method  Digital Logic Method 1 0 1 0 0 0 1 1 0 1 01110 FCS or F (n-k) D (k) T (n) 110101 P (n-k+1)

23. COE 341 – Dr. Marwan Abu-Amara 23 Modulo 2 Arithmetic Binary arithmetic without carry Equivalent to XOR operation i.e:  0  0 = 0; 1  0 = 1; 0  1 = 1; 1  1 = 0  1  0 = 0; 0  1 = 0; 1  1 = 1 Examples: 1010 +1010 ___________ 0000

24. COE 341 – Dr. Marwan Abu-Amara 24 CRC Error Detection Process Given k-bit data (D), the TX generates an (n – k)-bit FCS field (F) such that the total n-bit frame (T) is exactly divisible by some (n-k+1)-bit predetermined devisor (P) (i.e. gives a zero remainder) In general, the received frame may or may not be equal, in value, to the sent frame  Let the received frame be (T’)  In error-free transmission T’ = T The RX then divides (T’) by the same known divisor (P) and checks if there is any remainder  If division yields a remainder then the frame is erroneous  If the division yields zero remainder then the frame is error- free unless many erroneous bits in T’ resulted in a new exact division by P (This is very unlikely but possible, causing an undetected error!)

25. COE 341 – Dr. Marwan Abu-Amara 25 CRC Generation Data D: T = 2 (n – k)  D + F LSB ? P is 1-bit longer than F (n-k) left shifts (multiplications by 2)

26. COE 341 – Dr. Marwan Abu-Amara 26 CRC Generation T = 2 (n – k)  D + F, What is F that makes T divides P exactly ? Claim: F is the remainder obtained from dividing {2 (n – k)  D} by divisor P where Q is the quotient and F is the remainder If this is the correct F, T should now divide P with Zero remainder Note: For F to be a remainder when dividing by P, it should be 1-bit smaller (1)

27. COE 341 – Dr. Marwan Abu-Amara 27 CRC Generation – Modulo-2 Arithmetic Method At TX: CRC Generation (using previous rules):  Multiply:2 (n – k)  D (left shift by (n-k) bits)  Divide:2 (n – k)  D / P  Use the resulting (n – k)-bit remainder as the FCS At RX: CRC Checking: RX divides the received T (i.e. T’) by the known divisor (P) and checks if there is any remainder

28. COE 341 – Dr. Marwan Abu-Amara 28 Example – Modulo-2 Arithmetic Method Given  D = 1 0 1 0 0 0 1 1 0 1  P = 1 1 0 1 0 1 Find the FCS field Solution:  First we note that: The size of the data block D is k = 10 bits The size of P is (n – k + 1) = 6 bits  Hence the FCS length is n – k = 5  Total size of the frame T is n = 15 bits

29. COE 341 – Dr. Marwan Abu-Amara 29 Example – Modulo-2 Arith. Method Solution (continued):  Multiply 2 (n – k)  D 2 (5)  1 0 1 0 0 0 1 1 0 1 = 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 This is a simple shift to the left by five positions  Divide 2 (n – k)  D / P (see next slide for details) 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 ÷ 1 1 0 1 0 1 yields:  QuotientQ = 1 1 0 1 0 1 0 1 1 0  RemainderR = 0 1 1 1 0  So, FCS = R = 0 1 1 1 0: Append it to D to get the full frame T to be transmitted  T = 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 M FCS

30. COE 341 – Dr. Marwan Abu-Amara 30 Example – Modulo-2 Arith. Method # of bits < # of bits in P,  result of division is 0 Checks you should do (exercise): - Verify correct operation, i.e. that 2 (n-k) D = P*Q + R - Verify that obtained T (101000110101110) divides P (110101) exactly (i.e. with zero remainder) = FCS = F

31. COE 341 – Dr. Marwan Abu-Amara 31 Problem 6-12 For P = 110011 & D = 11100011, find the CRC

32. COE 341 – Dr. Marwan Abu-Amara 32 Chances of missing an error by CRC error detection Let E be an n-bit number with a bit = 1 at the position of each error bit error occurring in T Error occurring in T causes bit reversal Bit reversal is obtained by XORing with 1 So, received T r = T  E Error is missed (not detected) if T r is divisible by P Since T is made divisible by P, this requires that E is also divisible by P!. That is a ‘ bit ’ unlikely!

33. COE 341 – Dr. Marwan Abu-Amara 33 CRC Generation – Polynomial Method A k-bit word (D) can be expressed as a polynomial D(x) of degree (k-1) in a dummy variable x, with:  The polynomial coefficients being the bit values  The powers of X being the corresponding powers of 2 b k-1 b k-2 … b 2 b 1 b 0  b k-1 X k-1 + b k-2 X k-2 + … + b 1 X 1 + b 0 X 0 where b i (k-1 ≤ i ≤ 0) is either 1 or 0 Example1: an 8 bit word D = 11011001 is represented as D(X) = x 7 +x 6 +x 4 +x 3 +1  Ignore polynomial terms corresponding to 0 bits in the number

34. COE 341 – Dr. Marwan Abu-Amara 34 CRC – Mapping Binary Bits into Polynomials Example2: What is x 4 D(x) equal to? x 4 D(x) = x 4 (x 7 +x 6 +x 4 +x 3 +1) = x 11 +x 10 +x 8 +x 7 +x 4, the equivalent bit pattern is 110110010000 (i.e. four zeros appended to the right of the original D pattern) Example3: What is x 4 D(x) + (x 3 +x+1)? x 4 D(x) + (x 3 +x+1) = x 11 +x 10 +x 8 +x 7 +x 4 + x 3 +x+1, the equivalent bit pattern is 110110011011 (i.e. pattern 1011 = x 3 +x+1 appended to the right of the original D pattern)

35. COE 341 – Dr. Marwan Abu-Amara 35 CRC Generation: The Polynomial Way T = 2 (n – k)  D + F T(X) = X (n – k)  D(X) + F(X) Binary Arithmetic Polynomial

36. COE 341 – Dr. Marwan Abu-Amara 36 CRC Calculation - Procedure 1. Shift pattern D(X), (n-k) bits to the left, i.e. perform the multiplication X (n-k) D(X) 2. Divide the new pattern by the divisor P(X) 3. The remainder of the division, R(X) (i.e. n-k bits), is taken as FCS 4. The frame to be transmitted T(X) is X (n-k) D(X) + FCS

37. COE 341 – Dr. Marwan Abu-Amara 37 Example of Polynomial Method  D = 1 0 1 0 0 0 1 1 0 1(k = 10)  P = 1 1 0 1 0 1(n – k + 1 = 6) n – k = 5  n = 15 Find the FCS field Solution:  D(X) = X 9 + X 7 + X 3 + X 2 + 1  P(X) = X 5 + X 4 + X 2 + 1  X 5 D(X)/P(X) = (X 14 + X 12 + X 8 + X 7 + X 5 )/(X 5 + X 4 + X 2 + 1) This yields a remainder R(X) = X 3 + X 2 + X (details on next slide) i.e. F = 01110 R is n – k = 5-bit long  Remember to indicate any 0 bits!

38. COE 341 – Dr. Marwan Abu-Amara 38 Example of Polynomial Method 1 0 1 0 0 0 1 1 0 101110 F = R D 110101 P T Insert 0 bits to make 5 bits

39. COE 341 – Dr. Marwan Abu-Amara 39 Choice of P(X) How should we choose the polynomial P(X) (or equivalently the divisor P)? The answer depends on the types of errors that are likely to occur in our communication link As seen before, an error pattern E(X) will be undetectable only if it is divisible by P(X) It can be shown that all the following error types are detectable :  All single-bit errors, if P(X) has two terms or more  All double-bit errors, if P(X) has three terms or more  Any odd number of errors, if P(X) contains the factor (X+1)  Any burst error whose length is less than the FCS length (n – k)  A fraction (=1-2 -(n-k-1) ) of error bursts of length (n-k+1)  A fraction (=1-2 -(n-k) ) of error bursts of length > (n-k+1)

40. COE 341 – Dr. Marwan Abu-Amara 40 Choice of P(X) In addition, if all error-patterns are equally likely, and r = n - k = length of the FCS, then:  For a burst error of length (r + 1), the probability of undetected error is 1/2 (r – 1)  For a longer burst error i.e. length > (r + 1), the probability of undetected error is 1/2 r There are four widely-used versions of P(X)  CRC-12:P(X) = X 12 + X 11 + X 3 + X 2 + X + 1 (r = 13 -1 = 12)  CRC-16:P(X) = X 16 + X 15 + X 2 + 1 (r = 17 -1 = 16)  CRC-CCITT:P(X) = X 16 + X 12 + X 5 + 1  CRC-32:P(X) = X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 (r = 33 -1 = 32) FCS is 1-bit shorter than P: FCS Size P(X) always starts with 1

41. COE 341 – Dr. Marwan Abu-Amara 41 Some CRC Applications CRC-8 and CRC-10 (not shown) are used in ATM CRC-12 is used for transmission of 6-bit characters. Its FCS length is 12-bits CRC-16 & CRC-CCITT are used for 8-bit characters in the US and Europe respectively  Used in HDLC CRC-32 is used for IEEE 802.3 LAN standard

42. COE 341 – Dr. Marwan Abu-Amara 42 CRC Generation – Digital Logic Data Block, D 1010001101 k = 10 (size of D) (known data to be TXed) n – k + 1 = 6 size of P (known divisor) P (X) = X 5 +X 4 +X 2 +1 (110101) n – k = 5 size of FCS (to be determined at TX) n = 15 5-element left-shift register Initially loaded with 0’s After n left shifts, register will contain the required FCS Divisor is “hardwired” as feedback connections via XOR gates into the shift register cells Starting at LSB, for the first (n-k) bits of P, add an XOR only for 1 bits Always An XOR at C 0 P = X 5 +X 4 +X 2 +X 0

43. COE 341 – Dr. Marwan Abu-Amara 43 CRC Generation at TX P = X 5 +X 4 +X 2 +X 0 FCS generated in the shift register after n (=15) shift steps C 0 in C 2 in C 4 in D Start with Shift Register Cleared to 0’s MSB Inputs formed with Combination Logic

44. COE 341 – Dr. Marwan Abu-Amara 44 CRC Checking at RX P = X 5 +X 4 +X 2 +X 0 C 0 in C 2 in C 4 in D MSB Start with Shift Register Cleared to 0’s Received Frame, T D FCS 0’s in the shift register after n (=15) shift steps (if no errors) Inputs formed with Combination Logic MSB 15 bits

45. COE 341 – Dr. Marwan Abu-Amara 45 Problem 6-13 A CRC is constructed to generate a 4-bit FCS for an 11-bit message. The generator polynomial is X 4 +X 3 +1 a) Draw the shift register circuit that would perform this task b) Encode the data bit sequence 10011011100 (leftmost bit is the LSB) using the generator polynomial and give the code word c) Now assume that bit 7 (counting from the LSB) in the code word is in error and show that the detection algorithm detects the error

46. COE 341 – Dr. Marwan Abu-Amara 46 Problem 6-13 – Solution a) Input data   C0C0 C1C1 C2C2 C3C3 b) Data (D) = 1 0 0 1 1 0 1 1 1 0 0 D(X) = 1 + X 3 + X 4 + X 6 + X 7 + X 8 X 4 D(X) = X 12 + X 11 + X 10 + X 8 + X 7 + X 4 T(X) = X 4 M(X) + R(X) = X 12 + X 11 + X 10 + X 8 + X 7 + X 4 + X 2 Code = 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 c)Code in error = 0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 yields a nonzero remainder  error is detected P(X) = X 4 +X 3 +1 LSB

47. COE 341 – Dr. Marwan Abu-Amara 47 Error Correction Once an error is detected, what action can RX take? (i.e. I found an error, now what? ) Two alternatives:  RX asks for a retransmission of the erroneous frame Adopted by data-link protocols such as HDLC and transport protocol such as TCP A Backward Error Correction (BEC) method  RX attempts to correct the errors if enough redundancy exists in the received data TX uses Block Coding to allow RX to correct potential errors A Forward Error Correction (FEC) method Use in applications that leave no time for retransmission, e.g. VoIP.

48. COE 341 – Dr. Marwan Abu-Amara 48 Error Correction vs. Error Control Backward error correction by retransmission is not recommended in the following cases:  Error rate is high (e.g. wireless communication) Will cause too much retransmission traffic  network overloading  Transmission distance is long (e.g. satellite, submarine optical fiber cables) Network becomes very inefficient (Not utilized properly) Usually:  Error Correction methods: Those that use FEC techniques  Error Control methods: Those that use retransmission