1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 426 - VLSI System Design Lecture 2 - Verilog Review January 29, 2003

2. 1/29/03ECE 426 - Lecture 22 Where we are...  Today:  Verilog Review  Verilog, Event-Driven Simulation, and Delays

3. 1/29/03ECE 426 - Lecture 23 Announcements  Class in AEC 400 until further notice  TA Position Available in ECE 323 Lab- See Dr. Rich  Reading  Wolf: 8.1-8.3  Breaking news:  Smaller chip companies combine efforts on new processes EE Times 1/13: AMD, IBM to collaborate on 65nm, 45nm EE Times 1/20: Motorola, Philips & STMicroelectronics collaborating on 90nm & 65nm development  Intel continues to go it alone (EE Times 1/20)

4. 1/29/03ECE 426 - Lecture 24 Major Topics this Semester  Advanced Verilog  Verilog Review  Event-Driven Simulation  Delays  Coding Styles for Synthesis and Large Designs  Behavioral Modeling  Testbenches and Verification  More about Chip Design  Group Design Project: Simplified Ethernet Design and Verification (WimpNet ‘03)

5. 1/29/03ECE 426 - Lecture 25 Review - ASIC Design Flow Synthesize Blocks / Timing Analysis Timing OK? Place & Route / Timing Analysis Timing OK? N N Y Y DONE START Physical DesignLogic Synthesis HDL InNetlist Out Layout Out (GDSII or CIF)

6. 1/29/03ECE 426 - Lecture 26 Verilog Review  Basic Module Syntax  Combinational Logic  Parameters  Module Instantiation  Sequential Logic  Finite State Machines

7. 1/29/03ECE 426 - Lecture 27 Verilog Background  Designed as a language for event-driven simulation  Synthesis added as an “afterthought  Only a subset can be synthesized  Synthesis tools try to match simulation behavior  So far, we’ve focused on the synthesis subset  Structural Descriptions - module instantiations  Behavioral Descriptions assign - continuous assignments always blocks

8. 1/29/03ECE 426 - Lecture 28 Verilog module construct  Key building block of language  declaration - specifies a module interface Input & output ports connections to outside world “black box” model - no details about internals  body - specifies contents of "black box" behavior - what it does structure - how it's built from other "black boxes"

9. 1/29/03ECE 426 - Lecture 29 Verilog Module Declaration  Describes the external interface of a single module  Name  Ports - inputs and outputs  General Syntax: module modulename ( port1, port2,... ); port1 direction declaration; port2 direction declaration; reg declarations; wire declarations; module body - “parallel” statements endmodule // note no semicolon (;) here!

10. 1/29/03ECE 426 - Lecture 210 Verilog Body Declaration - “Parallel” Statements  Parallel statements describe concurrent behavior (i.e., statements which “execute” in parallel)  Types of Parallel Statements:  assign - used to specify simple combinational logic  always - used to specify repeating behavior for combinational or sequential logic  initial - used to specify startup behavior (not supported in synthesis - but useful in simulation!)  module instantiation - used for structure  … and other features useful only in simulation

11. 1/29/03ECE 426 - Lecture 211 Verilog Data Types  nets - describe “wire” connections  general purpose: wire  special purpose: supply0, supply1, tri0, tri1, triand, trior, trireg, wand, wor  registers - variables (assigned values by procedural statement)  reg - basic binary values  integer - binary word (≥32 bits - machine dependent)  real - floating point (not supported by synthesis)  time - simulation time (not supported in synthesis)  realtime - simulation time (not supported in synthesis)

12. 1/29/03ECE 426 - Lecture 212 Verilog Logic Values  Each wire or register type can take on 4 values:  0 - Standard binary “FALSE”  1 - Standard binary “TRUE”  X - UNKNOWN  Z - High Impedance  During simulation, all variables originally X  Complication: x & z sometimes used as “wildcards” (e.g. casex, casez )

13. 1/29/03ECE 426 - Lecture 213 More about Data Types  Vectors - Multiple-Bit Signals (net or register) wire [31:0] sum; reg [7:0] avg;  Arrays - used for memories reg [7:0] memory [0:255];  Strings - vector sized to hold ASCII constant “a string” word size memory size 64-bit vector

14. 1/29/03ECE 426 - Lecture 214 Data Types and Module Ports  Input ports must always be a wire (net)  Output ports can be wire or reg always @(a or b) x = a ^ b; assign y = ~a; xor(z,b,c) (instantiation) a b c x y z wire reg wire

15. 1/29/03ECE 426 - Lecture 215 Comb. Modeling with assign  Used for simple logic functions module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule

16. 1/29/03ECE 426 - Lecture 216 Combinational Modeling with always  Motivation  assign statements are fine for simple functions  More complex functions require procedural modeling  Basic syntax: always (sensitivity-list) statement or always (sensitivity-list) begin statement-sequence end Signal list - change activates block Procedural statement ( =, if/else, etc.) Compound Statement - sequence of statements

17. 1/29/03ECE 426 - Lecture 217 Combinational Modeling with always  Example: 4-input mux behavioral model module mux4(d0, d1, d2, d3, s, y); input d0, d1, d2, d3; input [1:0] s; output y; reg y; always @(d0 or d1 or d2 or d3 or s) case (s) 2'd0 : y = d0; 2'd1 : y = d1; 2'd2 : y = d2; 2'd3 : y = d3; default : y = 1'bx; endcase Endmodule Blocking assignments (immediate update)

18. 1/29/03ECE 426 - Lecture 218 Review Questions:  What are these pitfalls?  Latch Inference  Missing inputs on sensitivity list

19. 1/29/03ECE 426 - Lecture 219 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module  Original mux2 module: module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; endmodule

20. 1/29/03ECE 426 - Lecture 220 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module module mux4(d0, d1, d2, d3, s, y); input[3:0]d0, d1, d2, d3; input[1:0]s; output [3:0]y; wire[3:0]low, high; mux2 lowmux(d0, d1, s[0], low); mux2 highmux(d2, d3, s[0], high); mux2 finalmux(low, high, s[1], y); endmodule Instance NamesConnections

21. 1/29/03ECE 426 - Lecture 221 Parameterized Modules  Parameters - define values that can change  Declaration: module mod1(in1, in2, out1, out2); parameter N=default-value; input [N-1 : 0] in1, in2; output [N-1 : 0] out1; … endmodule  Instantiation: wire [7:0] w, x, y; wire z; mod1 #(8) my_mod1(w,x,y,z); Defines Parameter N Uses Parameter NSets Parameter N for instance my_mod1 Sizes must match instantiated value!

22. 1/29/03ECE 426 - Lecture 222 Parameterized Modules: Example  N-bit 2-1 multiplexer (parameterized bitwidth) module mux2( sel, a, b, y ); parameter bitwidth=32; input sel; input [bitwidth-1:0] a, b; output [bitwidth-1:0] y; assign y = sel ? b : a; endmodule  Instantiations mux2 #(16) my16bit_mux(s, a,b, c); mux2 #(5) my5bit_mux(s, d, e, f); mux2 #(32) my32bit_mux(s, g, h, i); mux2 myDefault32bit_mux(s, j, k, l); Defines Parameter bitwidth (default value: 32 ) Uses Parameter bitwidth to set input, output size

23. 1/29/03ECE 426 - Lecture 223 Symbolic Constants with Parameters  Idea: use parameter to name “special constants” parameter RED_ALERT = 2’b11; parameter YELLOW_ALERT = 2’b01; parameter GREEN_ALERT = 2’b00;  Don’t change in module instances  Do this to make your code more understandable  For others reading your code  For yourself reading your code after some time has passed

24. 1/29/03ECE 426 - Lecture 224 Sequential Design in Verilog - Basic Constructs  Describe edge-triggered behavior using:  always block with“edge event” always @(posedge clock-signal) always @(negedge clock-signal)  Nonblocking assignments ( <= ) @always(posedge clock-signal) begin output1 <= expression1;... output2 <= expression2;... end Registered Outputs for positive edge-trigger for negative edge-trigger Non-Blocking Assignments (deferred update)

25. 1/29/03ECE 426 - Lecture 225 always @(inputlist) or assign always@(posedge clock) Combining Sequential and Combinational Outputs  General circuit - both registered and comb. outputs  Approach: multiple always blocks or assign statements

26. 1/29/03ECE 426 - Lecture 226 Registered Output Combinational Output Example: Adding carry to 4-bit Counter module counter(clk, Q, carry); input clk; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); always @( posedge clk ) begin Q <= Q + 1; end endmodule

27. 1/29/03ECE 426 - Lecture 227 Review Question: What Happens Here? module counter(clk, Q, carry); input clk; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value reg carry; always @( posedge clk ) begin carry <= (Q == 4'b1111); Q <= Q + 1; end endmodule

28. 1/29/03ECE 426 - Lecture 228 State Machine Design  Traditional Approach:  Create State Diagram  Create State Transition Table  Assign State Codes  Write Excitation Equations & Minimize  HDL-Based State Machine Design  Create State Diagram (optional)  Write HDL description of state machine  Synthesize

29. 1/29/03ECE 426 - Lecture 229 Coding FSMs in Verilog - “Explicit” Style  Clocked always block - state register  Combinational always block -  next state logic  output logic

30. 1/29/03ECE 426 - Lecture 230 Coding FSMs in Verilog - Code Skeleton  Part 1 - Declarations module fsm(inputs, outputs); input...; reg...; parameter [NBITS-1:0] S0 = 2'b00; S1 = 2'b01; S2 = 2b'10; S3 = 2b'11; reg [NBITS-1 :0] CURRENT_STATE; reg [NBITS-1 :0] NEXT_STATE; State Codes State Variable

31. 1/29/03ECE 426 - Lecture 231 Coding FSMs in Verilog - Code Skeleton  Part 2 - State Register, Logic Specification always @(posedge clk) begin CURRENT_STATE <= NEXT_STATE; end always @(CURRENT_STATE or xin) begin case (CURRENT_STATE) S0:... determine NEXT_STATE, outputs S1 :... determine NEXT_STATE, outputs end case end // always endmodule

32. 1/29/03ECE 426 - Lecture 232 Verilog and Event-Driven Simulation  Key idea: model circuit operation as sequence of events that take place at specific times  Input events - when input changes  Output events - response to input events (only generated when output changes) A B C A B C delay=4 input event output event

33. 1/29/03ECE 426 - Lecture 233 Event-Driven Simulation  Example: Modeling and AND Gate  Input events: changes on A, B input net  Output events: changes on C output net after delay A B C A B C t=5 A=1 t=17 B=1 t=33 B=0 t=29 C=1 delay=12 t=45 C=0 Input Events Output Events

34. 1/29/03ECE 426 - Lecture 234 Event-Driven Simulation  Output events from AND = input events for OR  Simulation time “jumps” from event to event A B C A B C delay=3 D E delay=4 D E

35. 1/29/03ECE 426 - Lecture 235 Notes about Event-Driven Simulation  Why use event-driven simulation? Because it's fast  Only model when signals change  Loss of accuracy: assumes ideal logical behavior  What are the alternatives?  Circuit simulation (e.g. PSpice) Numerical model of continuous behavior More accurate, but slower  Cycle-Level Compiled code simulation Model behavior in each clock cycle Faster, but doesn’t model dlay

36. 1/29/03ECE 426 - Lecture 236 Event-Driven Simulation (cont'd)  Processing Events - Data Structures  Event - specifies time event will occur net where signal will change new value of net  Event Queue - data structure that sorts events by time front of queue - earliest event back of queue - latest event also called a timing wheel

37. 1/29/03ECE 426 - Lecture 237 Event-Driven Simulation - Algorithm  Processing Events - Simulation Algorithm initialization: set all nets & regs to ‘x’ while (event queue not empty) { current_event = "earliest" event in queue; current_time = current_event.time; current_event.net.value = current_event.value; for (each module input connected to net) { evaluate(module) if output of module changes { create new event to represent output change add new event to queue } } }

38. 1/29/03ECE 426 - Lecture 238 Verilog Simulation Model  assign statement  executes when event changes any input  produces output event when output values changes  always block  executes when event changes variable in sensitivity list  produces output events when outputs change assign y = ~a; always @(a or b) x = a ^ b;

39. 1/29/03ECE 426 - Lecture 239 Coming Up  Delay Modeling in Verilog  Other Verilog Features  tasks & functions  system tasks  Verilog coding styles  Behavioral Modeling  Testbenches and Verification

40. 1/29/03ECE 426 - Lecture 240 Outline - Introduction to Verilog  Goals of HDL-Based Design  Verilog Background  A First Example  Module and Port Declarations  Modeling with Continuous Assignments  Some Language Details  Modeling with Hierarchy  Modeling with always blocks (combinational logic)  Demonstration: Using Verilogger  Discuss Project 1  Summary

41. 1/29/03ECE 426 - Lecture 241 HDL Overview  What is an HDL? A language for  simulation - “event driven” model of execution  synthesis - generates designs that match simulated behavior for a subset of the language  Common HDLs:  Verilog HDL  VHDL - VHSIC (Very High-Speed IC) HDL  SystemC - C++ with class libraries to support System-Level Design and Hardware Design

42. 1/29/03ECE 426 - Lecture 242 Verilog Simulators  On Windows Machines: Synapticad Verilogger (formerly veriwell)  Available on PCs in DSP & Electronics Labs  OR download from class website  OR borrow CD  To run: Programs->Synapticad/Verilogger Pro  On the Sun Workstation: Synopsys vcs / virsim  vcs -RI  On Windows NT Machines: Cadence Verilog  Installed, but haven’t used yet

43. 1/29/03ECE 426 - Lecture 243 Verilog module construct  Key building block of language  declaration - specifies a module interface Input & output ports connections to outside world “black box” model - no details about internals  body - specifies contents of "black box" behavior - what it does structure - how it's built from other "black boxes"

44. 1/29/03ECE 426 - Lecture 244 A First Example  Full Adder: module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Ports Port Declarations Semicolon NO Semicolon Continuous Assignment Statements

45. 1/29/03ECE 426 - Lecture 245 Comments about the First Example  Verilog describes a circuit as a set of modules  Each module has input and output ports  Single bit  Multiple bit - array syntax  Each port can take on a digital value (0, 1, X, Z) during simulation  Three main ways to specify module internals  Continuous assignment statements - assign  Concurrent statements - always  Submodule instantiation (hierarchy)

46. 1/29/03ECE 426 - Lecture 246 Bitwise Operators  Basic bitwise operators: identical to C/C++/Java module inv(a, y); input[3:0]a; output [3:0]y; assign y = ~a; endmodule Unary Operator: NOT 4-bit Ports

47. 1/29/03ECE 426 - Lecture 247 Reduction Operators  Apply a single logic function to multiple-bit inputs module and8(a, y); input[7:0]a; output y; assign y = &a; endmodule Reduction Operator: AND

48. 1/29/03ECE 426 - Lecture 248 Conditional Operators  Like C/C++/Java Conditional Operator module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; // if s=1, y=d1, else y=d0 endmodule Comment

49. 1/29/03ECE 426 - Lecture 249 More Operators  Equivalent to C/C++/Java Operators  Arithmetic: + - * / &  Comparison: == != >=  Shifting: >  Example: module adder(a, b, y); input[31:0]a, b; output[31:0]y; assign y = a + b; endmodule  Small expressions can create big hardware!

50. 1/29/03ECE 426 - Lecture 250 Bit Manipulation: Concatenation  { } is the concatenation operator module adder(a, b, y, cout); input[31:0]a, b; output[31:0]y; output cout; assign {cout,y} = a + b; endmodule Concatenation (33 bits)

51. 1/29/03ECE 426 - Lecture 251 Bit Manipulation: Replication  { n {pattern} } replicates a pattern n times module signextend(a, y); input[15:0]a; output [31:0]y; assign y = {16{a[15]}, a[15:0]}; endmodule Copies sign bit 16 times Lower 16 Bits

52. 1/29/03ECE 426 - Lecture 252 Internal Signals  Declared using the wire keyword module fulladder(a, b, cin, s, cout); inputa, b, cin; output s, cout; wireprop, gen; assign prop = a ^ b; assign gen = a | b; assign s = prop ^ cin; assign cout = gen | (cin & prop); endmodule

53. 1/29/03ECE 426 - Lecture 253 Some Language Details  Syntax - See Quick Reference Card  Major elements of language:  Lexical Elements (“tokens” and “token separators”)  Data Types and Values  Operators and Precedence  Syntax of module declarations

54. 1/29/03ECE 426 - Lecture 254 Verilog Lexical Elements  Whitespace - ignored except as token separators  blank spaces  tabs  newlines  Comments  Single-line comments //  Multi-line comments /* … */  Operators- unary, binary, ternary  Unary a = ~b;  Binary a = b && c;  Ternary a = (b < c) ? b : c;

55. 1/29/03ECE 426 - Lecture 255 Verilog Numbers  Sized numbers: '  - decimal number specifying number of bits  - base of number decimal 'd or 'D hex 'h or 'H binary ‘b or ‘B  - consecutive digits normal digits 0, 1, …, 9 (if appropriate for base) hex digitsa, b, c, d, e, f x "unknown" digit z "high-impedance" digit  Examples 4’b111112’h7af16’d255

56. 1/29/03ECE 426 - Lecture 256 Verilog Numbers (cont'd)  Unsized numbers  Decimal numbers appearing as constants (236, 5, 15, etc.)  Bitwidth is simulator-dependent (usually 32 bits)  Negative numbers  sized numbers: '-' before size -8'd127 -3'b111  unsized numbers: '-' before first digit -233  As in VHDL, underline '_' can be used as a "spacer 12'b00010_1010_011 is same as 12'b000101010011

57. 1/29/03ECE 426 - Lecture 257 Verilog Strings  Anything in quotes is a string: "This is a string" "a / b"  Strings must be on a single line  Treated as a sequence of 1-byte ASCII values  Special characters - C-like (\)

58. 1/29/03ECE 426 - Lecture 258 Verilog Identifiers  Starting character: alphabetic or '_'  Following characters: alpha, numeric, or '_'  Examples: george_paul  "Escaped" identifiers:  start with backslash  follow with any non-whitespace ASCII  end with whitespace character  Examples: \212net\**xyzzy**\$foo  Special notes:  Identifiers are case sensitive  Identifiers may not be reserved words

59. 1/29/03ECE 426 - Lecture 259 Verilog Reserved Words alwaysandassignbeginbufbufif0bufif1 case casexcasezcmos deassigndefaultdefparamdisableedge elseendendcaseendfunctionendmodule endprimitiveendspecifyendtableendtaskeventfor forceforeverforkfunctionhighz0highz1ififnone initialinoutinputintegerjoinlargemacromodule mediummodulenandnegedgenmosnor not notif0notiforoutputparameterpmos posedgeprimitivepull0pull1pulldownpulluprcmos realrealtimeregreleaserepeatrnmosrpmosrtran rtranif0rtranif1scalaredsmallspecifyspecparamstrong0 strong1supply0supply1tabletasktimetrantranif0 tranif1tritri0tri1triandtriortriregvectored waitwandweak0weak1whilewireworxnor xor

60. 1/29/03ECE 426 - Lecture 260 Verilog Data Types  Nets - connections between modules  input, output ports  wires - internal signals  Other types: wand, wor, trior, trireg (ignore for now)  Advanced Data Types (more later)  Vectors - multiple bit wires, registers, etc.  reg - Variables that are assigned values  Arrays and Memories  Parameters

61. 1/29/03ECE 426 - Lecture 261 Operators and Precedence  Override with parentheses () when needed

62. 1/29/03ECE 426 - Lecture 262 Verilog Module Declaration  Describes the external interface of a single module  Name  Ports - inputs and outputs  General Syntax: module modulename ( port1, port2,... ); port1 direction declaration; port2 direction declaration; reg declarations; module body - “parallel” statements endmodule // note no semicolon (;) here!

63. 1/29/03ECE 426 - Lecture 263 Verilog Body Declaration - “Parallel” Statements  Parallel statements describe concurrent behavior (i.e., statements which “execute” in parallel)  Types of Parallel Statements:  assign - used to specify simple combinational logic  always - used to specify repeating behavior for combinational or sequential logic  initial - used to specify startup behavior (not supported in synthesis)  module instantiation - used for structure  … and other features we’ll talk about later

64. 1/29/03ECE 426 - Lecture 264 Combinational Modeling with always  Motivation  assign statements are fine for simple functions  More complex functions require procedural modeling  Basic syntax: always (sensitivity-list) statement or always (sensitivity-list) begin statement-sequence end Signal list - change activates block Procedural statement ( =, if/else, etc.) Compound Statement - sequence of statements

65. 1/29/03ECE 426 - Lecture 265 Combinational Modeling with always  Example: 4-input mux behavioral model module mux4(d0, d1, d2, d3, s, y); input d0, d1, d2, d3; input [1:0] s; output y; reg y; always @(d0 or d1 or d2 or d3 or s) case (s) 2'd0 : y = d0; 2'd1 : y = d1; 2'd2 : y = d2; 2'd3 : y = d3; default : y = 1'bx; endcase endmodule

66. 1/29/03ECE 426 - Lecture 266 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module  Original mux2 module: module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; endmodule

67. 1/29/03ECE 426 - Lecture 267 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module module mux4(d0, d1, d2, d3, s, y); input[3:0]d0, d1, d2, d3; input[1:0]s; output [3:0]y; wire[3:0]low, high; mux2 lowmux(d0, d1, s[0], low); mux2 highmux(d2, d3, s[0], high); mux2 finalmux(low, high, s[1], y); endmodule Instance NamesConnections

68. 1/29/03ECE 426 - Lecture 268 Larger Hierarchy Example  Use full adder to create an n-bit adder module add8(a, b, sum, cout); input [7:0] a, b; output [7:0] sum; output cout; wire [7:0] c; // used for carry connections assign c[0]=0; fulladder f0(a[0], b[0], c[0], sum[0], c[1]); fulladder f1(a[1], b[1], c[1], sum[1], c[2]); fulladder f2(a[2], b[2], c[2], sum[2], c[3]); fulladder f3(a[3], b[3], c[3], sum[3], c[4]); fulladder f4(a[4], b[4], c[4], sum[4], c[5]); fulladder f5(a[5], b[5], c[5], sum[5], c[6]); fulladder f6(a[6], b[6], c[6], sum[6], c[7]); fulladder f7(a[7], b[7], c[7], sum[7], cout); endmodule

69. 1/29/03ECE 426 - Lecture 269 Hierarchical Design with Gate Primitives  “Built-In” standard logic gates and or not xor nand nor xnor  Using Gate Primitives: and g1(y, a, b, c, d);  How are the different from operators ( &, |, ~, etc.)?  Operators specify function  Gate primitives specify structure Output Inputs (variable number)

70. 1/29/03ECE 426 - Lecture 270 Gate Primitives Example  2-1 Multiplexer module mux2s(d0, d1, s, y); wire sbar, y0, y1; not inv1(sbar, s); and and1(y0, d0, sbar); and and2(y1, d1, s); or or1(y, y0, y1); endmodule;  Why shouldn’t we use gate primitives?  Requires “low-level” implementation decisions  It’s usually better to let synthesis tools make these

71. 1/29/03ECE 426 - Lecture 271 Lab 8 - Comb. Design with Verilog  Prelab: write out case statement by hand for binary decoder  In the lab:  Type in and simulate binary decoder using Verilogger  FTP to workstations & synthesize using Synopsys tools

72. 1/29/03ECE 426 - Lecture 272 Demonstration: Using Verilogger  Starting Verilogger  Start->Program Files->Synapticad->Verilogger Pro  Key Windows:  Project Manager  HDL Editor Windows  Timing Diagram Window  Creating and Simulating a Verilog file  Editor->New HDL File  Editor->Save HDL File As...  Project->Add File to Project  Simulate->Build (yellow button)  Simulate->Run (green “play” button)

73. 1/29/03ECE 426 - Lecture 273 Using Verilogger  Create new project: Project->New Project  Create HDL File(s): Editor->New HDL File  Run Simulator: Simulate->Run  Edit timing diagram to control input stimulus / observe response  Timing diagram is represented as a separate verilog file