1. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 2 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic) - Counters Interconnect - Switches - Arbiters - Bus

3. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 3 An Intel Microprocessor Itanium has 6 integer execution units like this

4. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 4 Bit-Sliced Design

5. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 5 Bit-Sliced Datapath

6. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 6 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

7. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 7 Adders

8. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 8 Full-Adder

9. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 9 The Binary Adder

10. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 10 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete =A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for C 1 = G 0 + P 0 C 0 C 2 = G 1 +P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 +P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0

11. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 11 The Ripple-Carry Adder Worst case delay is linear with the number of bits Goal: Make the fastest possible carry path circuit FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 A 3 B 3 S 3 C i,0 C o (  C i,1 ) C o C o,2 C o,3 t d = O(N) t adder = (N-1)t carry + t sum

12. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 12 Complimentary Static CMOS Full Adder 28 Transistors Not so good for the carry chain 3 PMOS in row

13. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 13 Inversion Property

14. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 14 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

15. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 15 A Better Structure: The Mirror Adder V DD S C o 24 transistors Since !C o drives 2 internal and 2 inverter transistor gates (to form C i for the next bit adder) should oversize the carry circuit. Use PMOS/NMOS ratio of 2.

16. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 16 Mirror Adder Stick Diagram

17. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 17 The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors in the carry-generation. In layout, the most critical is the reduction of the capacitance at node C o. (including the diffusion capacitances.) C o has four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for speed. All transistors in the sum stage can be minimal size.

18. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 18 Complementary Pass Transistor Logic FA A !A B!B C in !C in !S S C out !C out A !A B !B BC in !C in C in !C in 20+8 transistors, dual rail – beware of threshold drops

19. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 19 Transmission Gate Full Adder Identical Delays for Carry and Sum

20. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 20 Manchester Carry Chain  Total delay of  time to form the switch control signals G i and P i  setup time for the switches  signal propagation delay through N switches in the worst case

21. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 21 Manchester Carry Chain

22. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 22 Manchester Carry Chain Stick Diagram

23. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 23 Carry-Bypass Adder Also called Carry-Skip Adder Since Kill and Generate are obtained in parallel, the worst delay is when propagate is needed - set by BP=1

24. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 24 Carry-Bypass Adder (cont.) t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum

25. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 25 Carry Ripple versus Carry Bypass

26. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 26 Carry-Select Adder  Precompute the carry out of each block for both carry_in = 0 and carry_in = 1 (can be done for all blocks in parallel) and then select the correct one This idea can be carried on in a logarithmic tree fashion to obtain the addition in log 2 (N) time (see conditional sum adder developed in Samboon, Taesopapong MS thesis A VLSI-nMOS Hardware Implementation of a High Speed Parallel Adder Ohio University 1986)

27. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 27 Carry Select Adder: Critical Path

28. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 28 Linear Carry Select

29. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 29 Square Root Carry Select

30. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 30 Conditional Sum Adder Idea Final result selected

31. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 31 Architecture of Conditional Sum Adder Architecture of Conditional Sum Adder Delay = t dF (full adder)+t dM (mux)+t ds (selector)*log 2 n

32. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 32 Transistor Level Design of Full Adder Notice only 18 transistors needed to produce sum and two carry bits and their inverses

33. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 33 Full Adder Layout

34. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 34 Four BitConditional Sum Adder Four Bit Conditional Sum Adder

35. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 35 Adder Delays - Comparison

36. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 36 LookAhead - Basic Idea C 1 = G 0 + P 0 C 0 C 2 = G 1 +P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 +P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0

37. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 37 Look-Ahead: Topology Expanding Lookahead equations: Expanding all the way In the pull down area :

38. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 38 Look-Ahead: Topology Expanding Lookahead equations: Expanding all the way In the pull up area: Expanding Lookahead equations In the complementary form we get: Notice error in the pullup presented in textbook

39. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 39 Logarithmic Look-Ahead Adder

40. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 40 Carry Lookahead Trees Can continue building the tree hierarchically.

41. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 41 Tree Adders 16-bit radix-2 Kogge-Stone tree

42. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 42 Tree Adders 16-bit radix-4 Kogge-Stone Tree

43. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 43 Sparse Trees 16-bit radix-2 sparse tree with sparseness of 2

44. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 44 Tree Adders Brent-Kung Tree

45. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 45 Multipliers

46. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 46 The Binary Multiplication

47. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 47 The Binary Multiplication x  Partial products Multiplicand Multiplier Result 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1

48. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 48 The Array Multiplier Partial products

49. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 49 The MxN Array Multiplier — Critical Path Critical Path 1 & 2

50. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 50 Carry-Save Multiplier

51. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 51 Multiplier Floorplan

52. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 52 Wallace-Tree Multiplier

53. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 53 Wallace-Tree Multiplier

54. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 54 Wallace-Tree Multiplier

55. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 55 (4,2) Counters  Built out of two (3,2) counters (just FA’s!)  all of the inputs (4 external plus one internal) have the same weight (i.e., are in the same bit position)  the internal output is carried to the next higher weight position (indicated by the ) (3,2) Note: Two carry outs - one “internal” and one “external”

56. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 56 Tiling (4,2) Counters  Reduces columns four high to columns only two high  Tiles with neighboring (4,2) counters  Internal carry in at same “level” (i.e., bit position weight) as the internal carry out (3,2)

57. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 57 Tiling (4,2) Counters  Reduces columns four high to columns only two high  Tiles with neighboring (4,2) counters  Internal carry in at same “level” (i.e., bit position weight) as the internal carry out (3,2)

58. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 58 4x4 Partial Product Array Reduction multiplicand multiplier partial product array reduced pp array (to CPA) double precision product  Fast 4x4 multiplication using (4,2) counters

59. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 59 4x4 Partial Product Array Reduction multiplicand multiplier partial product array reduced pp array (to CPA) double precision product  Fast 4x4 multiplication using (4,2) counters

60. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 60 8x8 Partial Product Array Reduction ‘icand ‘ier partial product array How many (4,2) counters minimum are needed to reduce it to 2 rows?

61. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 61 8x8 Partial Product Array Reduction ‘icand ‘ier partial product array reduced partial product array How many (4,2) counters minimum are needed to reduce it to 2 rows? Answer: 24

62. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 62 Multipliers —Summary

63. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 63 Shifters

64. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 64 The Binary Shifter

65. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 65 A Programmable Binary Shifter rgtnopleft AiAi A i-1 B i-1 BiBi AiAi A i-1 rgtnopleftBiBi B i-1 A1A1 A0A0 010A1A1 A0A0 A1A1 A0A0 1000A1A1 A1A1 A0A0 001A0A0 0

66. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 66 The Barrel Shifter Sh3Sh2Sh1Sh0 Sh3 Sh2 Sh1 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 : Control Wire : Data Wire Area Dominated by Wiring Example: Sh0 = 1 B 3 B 2 B 1 B 0 = A 3 A 2 A 1 A 0 Sh1 = 1 B 3 B 2 B 1 B 0 = A 3 A 3 A 2 A 1 Sh2 = 1 B 3 B 2 B 1 B 0 = A 3 A 3 A 3 A 2 Sh3 = 1 B 3 B 2 B 1 B 0 = A 3 A 3 A 3 A 3

67. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 67 4x4 barrel shifter Width barrel ~ 2 p m M

68. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 68 8-bit Logarithmic Shifter (part)

69. EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 69 A 3 A 2 A 1 A 0 Out3 Out2 Out1 Out0 0-7 bit Logarithmic Shifter