2. Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel Corporation, USA Alex KondratyevTheseus Logic, USA Luciano LavagnoUniversità di Udine, Italy Alexander YakovlevUniversity of Newcastle upon Tyne, UK

3. STATESTATE Combinational Logic Clock Inputs Outputs Current state Next state f -1

4. STATESTATE Combinational Logic Inputs Outputs Current state Next state

5. Combinational Logic Inputs Outputs Current state Next state

7. 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

8. 1 1 0 0 0 0 0 1 1 0 0 X 0 0 0 0 0

9. 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0

10. 1 1 0 X 0 0 0 1 1 0 0 1 0 0 0 0 0

11. 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0

12. 1 1 0 1 0 0 X 1 1 0 0 1 0 0 0 0 0

13. 1 1 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0

14. 1 1 X 1 0 0 1 1 1 0 0 1 0 0 0 0 0

15. 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0

16. 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0

17. 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 X

18. 1 1 1 1 0 0 1 1 1 0 1 1 0 0 0 0 1

19. 1 1 1 1 0 0 1 1 1 0 1 1 X 0 0 0 1

20. 1 1 1 1 0 0 1 1 1 0 1 1 1 0 0 0 1

21. 1 1 1 1 0 0 1 1 1 0 1 1 1 0 0 X 1

22. 1 1 1 1 0 0 1 1 1 0 1 1 1 0 0 1 1

23. 1 1 1 1 0 0 1 1 1 0 1 1 1 X 0 1 1

24. 1 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1

25. 1 1 1 1 0 0 1 1 1 0 1 1 1 1 X 1 1

26. 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1

27. A circuit is a concurrent system Gates  Processes Delays  Computation times Signal transitions  Events

28. y- a+b+ x+y+ c+ c- a- b- x- x+y- y+x- a b x y c Specification (environment) Implementation (circuit)

29. Outline Synthesis flow –Specification –State graph and next-state functions –State encoding –Implementability conditions –Logic decomposition Backannotation (theory of regions) Formal verification

30. x y z Signal Transition Graph (STG) x y z x+ x- y+ y- z+ z-

31. x y z x+ x- y+ y- z+ z-

32. x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y-

33. xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y- Next-state functions

34. x z y

35. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

36. VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

37. STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

38. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

39. Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

40. Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+ 10000 10010 10110 0111001110 01100 00110 10110 (DSr, DTACK, LDTACK, LDS, D)

41. QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

42. Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1  1 10110

43. Karnaugh map for LDS DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 000000/1? 1 111 - - - --- ---- - ---- ---

44. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

45. Concurrency reduction LDS- LDS+ LDS- 10110 DSr+

46. Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

47. State encoding conflicts LDS- LDTACK- LDTACK+ LDS+ 10110

48. Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC+ 101101 101100

49. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

50. Complex-gate implementation

51. Implementability conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

52. Persistency 100000001 a- c+ b+b+ b+b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

53. a+ b+ c+ d+ a- b- d- a+ c-a- 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+

54. 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 ER(d+) ER(d-)

55. ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ a c d

56. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

57. No Hazards a b c x 0 abcx 1000 1100 b+ 0100 a- 0110 c+ 1 1 0 0 1 1 0 1 0 1 0 0

58. Decomposition May Lead to Hazards abcx 1000 1100 b+ 0100 a- 0110 c+ a b z c x 1 0 0 0 0 1000 1100 0100 0110 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 1 0 1 0

59. y- z-w- y+x+ z+ x- w+ 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Decomposition example

60. yz=1 yz=0 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ C C x y x y w z x y z y z w z w z y

61. s- s+ s- s=1 s=0 10011011 1000 1010 0111 0011 y+ x- w+ z+ z- 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 C C x y x y w z x y z w z w z y s y-

62. z-w- y+x+ z+ x- w+ s- s+ s- s+ s- s=1 s=0 10011011 1000 1010 0111 0011 y+ x- w+ z+ z- 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 y-

63. Event insertion a b c

64. a b ER(x) c

65. Event insertion a b ER(x) c x x x x b SR(x)

66. Event insertion b ER(x) c x x x x b SR(x) a

67. Properties to preserve a a b b a a b b a a b b x a a b b a a b b b a a b b x x a is persistent a is disabled by b = hazards

68. Interactive design flow Petri Net (STG) Transition System Transition System Reachability analysis Transformations + Synthesis

69. Synthesis of Petri Nets a a b b b c c c a bc Theory of regions (Ehrenfeucht, Rozenberg, 90) a b b c c

70. b b b b Label splitting a cc d d d d a b b c d

71. Formal verification Implementability properties –Consistency, persistency, state coding … Behavioral properties (safeness, liveness) –Mutual exclusion, “ack” after “req”, … Equivalence checking –Circuit  Specification –Circuit < Specification

72. Property verification: consistency d+ a+ b+ c-a- b-d- c+ Specification a+ a- Property Failure if a+ enabled in specification and a- enabled in property (or viceversa)

73. Correctness: environment  circuit d+ a+ b+ c-a- b-d- c+ a b c d Environment Circuit Failure: circuit produces an event unexpected (not enabled) by the environment

74. Fighting the state explosion Symbolic methods (BDDs) Partial order reductions Petri net unfoldings Structural theory (invariants)

75. Fighting with state explosion p1 p2 p3 p1 p2 p3 p1 p2 p3 0 1 0 1 0 0 0 0 1 1 1 1

76. Representing Markings p1p1 p2p2 p3p3 p4p4 p5p5 p0p0 p 2 + p 3 + p 5 = 1 p 0 + p 1 + p 4 + p 5 = 1 { p 0, p 3 }  v 0 v 1 v 2 v 3 p 2  v 0 v 1 p 3  v 0 v 1 p 5  v 0 p 0  v 2 v 3 p 1  v 2 v 3 p 4  v 2 Place encoding

77. Conclusions The synthesis and formal verification of asynchronous control circuits can be totally automated Existing tools at academia (http://www.lsi.upc.es/~jordic/petrify) An asynchronous circuit is a concurrent system with processes (gates) and communication (wires) The theory of concurrency is crucial to formalize automatic synthesis and verification methods

78. Food for theoreticians How to insert events (and signals) while preserving some properties (persistency, obs. equiv.) ? How to transform specifications and do incremental analysis ?. For example, recalculate –covers of S-components and T-components –symbolic representations of the state space Can we go beyond Free-Choice PNs for structural derivation of the (approximate) state space ? How to transform an unbounded partial specification into a bounded (and highly concurrent) implementable specification ? How to verify huge timed systems ?