1. The New FPGA Architecture by Applying The CS-Box Structure Zhou Lin, Catherine October 13, 2003

2. Outline  Introduction to the Xilinx FPGA architecture  Introduction to the CS-box structure –Preliminaries –The connection way of pad pins and wire segments. –The connection way of logic block pins and wire segments.

3. Outline  Experimental results –Channel width –Routing area  Future work

4. Introduction to The Xilinx FPGA Architecture

5. Introduction to The CS- Box Structure  Based on the Xilinx FPGA architecture.  Combines the connection box and the switch box to form the connection-switch box (CS-box). LL LL CS

6. Introduction to The CS- Box Structure (cont’)  Two types of switches in the CS-box –Those connecting one wire segment to another.  They are set in the same way as in the switch box in the Xilinx FPGA. –Those connecting one pin to one wire segment or vice versa.  The way to set them is the main topic in our research.

7. Introduction to The CS- Box Structure (cont’)  Two types of CS-boxes –Containing the switches that connect pad pins to wire segments or vice versa. –Containing the switches that connect logic block pins to wire segments or vice versa.

8. Introduction to The CS- Box Structure (cont’)  Preliminaries –W: Channel width. The number of wire segments in one channel. –Fc_pad: The number of wire segments each pad pin can be connected to. –Fc_input: The number of wire segments each input logic pin can be connected to. –Fc_output: The number of wire segments each output logic pin can be connected to. –P: The number of non-global pins on each logic block or pad.

9. The Connection Way of Pad Pins and Wire Segments  Fc_pad = W  for i:=1 to Fc_pad if i is even Set on the switch connecting the pin to the ith track in the x- directed channel. else Set on the switch connecting the pin to the ith track in the y- directed channel. endfor PadL L 0 1 2

10. The Connection Way of Logic Block Pins and Wire Segments  if W mod P = 0 flag = 0; else m = W / P; flag = 1; for i:=1 to P Connect the pin to the tracks with the number ki, where k=1, 2, …, m; if flag=1 Connect the pin to the track with the number [(m+1)i-W]; endfor L CS i=2 22 2 W = 3 & P = 2  m = 1 & flag = 1 i = 2

11. Experimental Results Xilinx & CS Routing Area No Buffer Sharing Buffer Sharing Circuit Name Channel Width Total Circuitper CLBTotal Circuitper CLB alu4 11 & 12 5.33045e+06 & 5825230 3331.53 & 3640.773.60349e+06 & 39627202252.18 & 2476.7 apex2 11 & 13 6.43963e+06 & 7039080 3326.25 & 3635.894.35160e+06 & 47868202247.73 & 2472.53 apex4 14 & 15 5.49633e+06 & 5709500 4240.99 & 4405.483.68954e+06 & 38625702846.87 & 2980.38 b9 4 & 4 160655 & 159813 1327.73 & 1320.77112001 & 112861925.631 & 932.736 bigkey 7 & 7 6.26076e+06 & 8650580 2147.04 & 2966.594.25262e+06 & 58583301458.37 & 2009.03 des 7 & 8 9.63926e+06 & 8598840 2428.64 & 2166.56.52320e+06 & 59131401643.54 & 1489.83 diffeq 8 & 10 3.71940e+06 & 4531920 2445.37 & 2979.572.52166e+06 & 30726401657.90 & 2020.15

12. Experimental Results (cont’) dsip 6 & 8 5.42644e+06 & 63271001860.92 & 2169.793.70137e+06 & 43527701269.33 & 1492.72 e64 8 & 9 722875 & 7947832501.30 & 2750.12493111 & 5468931706.27 & 1892.36 ex5p 14 & 15 4.62635e+06 & 48046104248.25 & 4411.953.10683+06 & 32515302852.92 & 2985.8 misex3 11 & 12 4.81514e+06 & 52613203334.58 & 3643.573.25587e+06 & 35798102254.76 & 2479.1 my_adder 4 & 4 67195.5 & 66254.91371.34 & 1352.1447389.6 & 47294.2967.134 & 965.189 s1423 5 & 6 357693 & 4414761589.75 & 1962.11250050 & 3076491111.33 & 1367.33 tseng 7 & 10 2.35760e+06 & 32538902164.92 & 2987.961.60510e+06 & 22078101473.92 & 2027.37 unreg 4 & 5 67195.5 & 770961371.34 & 1573.3947389.6 & 54754.1967.134 & 1117.43 Total 121 & 137 55486974 & 61541492.9 37689.95 & 41966.6 37561181.2 & 41917591.3 26635.019 & 28708.655 Incease 13.22%10.91%11.35%11.60%7.79%

13. Future  Do more experiments –Set Fc_pad, Fc_input and Fc_output equal to W / 2. –Apply different switch box structures into the FPGA with CS-boxes.