1. Frame-Level Pipelined Motion Estimation Array Processor Surin Kittitornkun and Yu Hen Hu IEEE Trans. on, for Video Tech., Vol. 11, NO.2 FEB, 2001

2. OUTLINE Methodology for VLSI Array Processors Design An Example on Frame Level Block Matching Algorithm

3. Design Levels Sequential Algorithm 1.DG Design 2.SFG Design 3.VLSI Array Design

5. Dependence Graph (DG)

6. DG: 1.Shift Invariant Shift-Unvariant DG for Sorting Algorithm For i from 1 to N For j from 1 to i m( i +1, j ) <- max[ x ( i, j ), m( i, j )] x( i, j +1) <- min[ x ( i, j ),m( i, j )]

7. DG: 2.Localization Broadcast vs. Transmittent Data

8. DG: 3.Reversible Arcs for Associative Operations If the operation used in the recursion is associative, then the directions of the arcs may be reversible.

9. DG: 4.Localization with Intermediate Variables Involved AR Filtering Algorithm

10. DG: 4.Localization with Intermediate Variables Involved AR Filtering Algorithm –Spiral Communication Approach –Local Communication Approach

11. Signal Flow Graph (SFG) Input(1) Output(1) Input(2) Output(2) D x(n) x(n-1)

12. SFG Projection Procedure For any projection direction, a processor space is orthogonal to the projection direction. Replace the arcs in the DG with zero or nonzero delay edges between their corresponding processors. Attach the input and output data to their corresponding processors.

13. Projection Example Insertion sorting Insertion Sorting Selection sorting Bubble sorting Selection Sorting Insertion Sorting

14. SFG to Systolic Array Replace Operation Node with PE. Place data and Input/Output pin with delay units.

15. Frame-Level Pipelined Motion Estimation Array Processor Surin Kittitornkun and Yu Hen Hu IEEE Trans. on, for Video Tech., Vol. 11, NO.2 FEB, 2001

16. Six-level nested Do-loop FSBM

17. Two-level nested Do-loop FSBM

19. k th -clock cycle (v-1)N h N 2 (h-1)N 2 (i-1)N j k th -clock cycle

20. 2D Localized DG of row 1, v =1 Search area and current frame coordinates of N v = 3; N h = 2; p =N/2 = 1. 2 p +1

21. Linear SFG of (2p + 1) 2 PEs, p = N/2 = 1 after systolic mapping of 2-D DG.

23. Systolic array with spiral interconnections

24. Microarchitecture of PE

25. Scheduled search area data

27. Performance