1. Motion Tracking Recorder 360 (MTR-360) Group #1 Lee Estep Philip Robertson Andy Schiestl Robert Tate

2. Original Objectives n Implement Modules and Interfaces n Update Interfaces for Second Camera n Develop Tracking Algorithm n Combine Interfaces into One System n Develop GUI for PC Interface n Deliverable – Security Camera System

3. Original Design Schematic Xilinx XC4010E (FPGA #2) ServoSet2 ServoSet1 64K SRAM IDE Interface PC Interface Servo Control FPGA Interface Memory Control IDE Hard Drive PC (Only needed for playback) QuickCam2 QuickCam1 64K SRAM Xilinx XC4010E (FPGA #1) Camera Interface Memory Control Algorithm FPGA Interface

4. Modifications to Plan n Using one 4028 FPGA n Only one camera used n Stepper motor for horizontal control n Less RAM

5. Final Design Schematic Xilinx XC4028E FPGA Algorithm Quick Cam PC (Only needed for playback) 32K SRAM IDE Hard Drive Servo Stepper Motor Servo Control Motor Control Camera Interface PC / Parallel Port Interface Memory Control / Interface IDE Interface

6. Board Layout gndvcc Camer a Parall el Port Parall el Port 4028 FPGA Camera Keyboard plug IDE port Parallel Buffer 1Parallel Buffer 2 IDE Buffer 2IDE Buffer 1IDE Buffer 3 Xilinx Xchecker 32K SRAM Demo-board 2Demo-board 1 Demo-board 3 Demo-board 6Demo-board 5Demo-board 4 Motor Driver

7. Accomplished n Completed and tested – Servo Control – Memory Control – Parallel port to PC n Initial Version Complete – Camera Interface – Stepper Motor n Under Construction – Algorithm – Hard Drive Control – GUI

8. Servo Control n Pulsegen generates a pulse between.46 ms and 2.1 ms n Divby divs the clock signal by ten or five 20 mS.465 to 2.1 mS

9. Stepper Control n Coundown is loaded with the angle n Stepstate actually counts through the control bits

10. Memory Control n Acts as a four-ported RAM – Parallel Port Interface – IDE Hard drive – Algorithm – Camera Interface n Use a State Machine to guarantee device access to memory

11. Memory Control II n Each device goes through a maximum of three states: 1. Check if device is requesting memory access 2. If yes, check whether read/write then set address to read/write 3. Set busy signal - Read or Write data from the device - then go to the next device 4. If No, check the next device n State diagram 1 2 3 4

12. PC Parallel port n Enables communication between the FPGA and a PC. n Used for viewing of stored images on the hard drive. 4 1 8 1 Data Error Data Strobe PC Parallel Interface (FPGA)

13. Camera Interface n Handles initialization of QuickCam n Not fully tested n Reads image from camera and stores to memory Memory Control Module Camera Interface Module QuickCam Address(15) MemAck Data(8) MemGo Nibble (4) PCAck Reset Command (8) CamRdy

14. Hard Drive Control 74 LS 245 74 LS 245 74 LS 245 IDE Hard Disk PIO Timing File System Support Image Transfer and Control Reset Logic 8 8 8 8 8 8 Direction Reset IDE Control Logic n Moves Images between memory and the hard disk n Stores time image was taken as well as the image itself n Allows random access of pictures and selective erasure

15. Algorithm n Concept tested using C program n Background independent if enough contrast n Flickering lights (60Hz) limit sensitivity Take 2 pictures Subtract values of corresponding pixels Differenc e <=1 Use 0 in future calc. More Pixels? Find leftmost and rightmost column where sum > threshold Find topmost and bottom most row where sum > threshold Move center of view toward midpoint of box defined previously No Yes No Yes

16. Member Responsibilities

17. Updated Time Chart

18. References n Texas Instruments – http://www.ti.com n Digi-Key – http://www.digikey.com n Xilinx – http://www.xilinx.com n Winbond – http://www.winbond.com n Vantec – http://www.vantec.com n CPSC 483 IDE Interface for E-Book Project Spring 1999 – http://www.cs.tamu.edu/course-info/cpsc483/common/99a/g3 n CPSC 483 Autonomous Tracking Unit Project Spring 1999 – http://www.cs.tamu.edu/course-info/cpsc483/common/99a/g1

19. Evaluation n Overall Project: 2 – Servo Control:3 – Stepper Control:2 – Hard drive control:1 – Memory Control:2 – Camera Control:2 – Algorithm:1 n Team Coordination:1 n Support from lab:3 – TA’s:2 – Materials:4