Presentation is loading. Please wait.

Presentation is loading. Please wait.

Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers."— Presentation transcript:

1 Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers University Tezaswi@caip.rutgers.edu Vishwani D. Agrawal, Agere Systems va@agere.com http://cm.bell-labs.com/cm/cs/who/va Michael L. Bushnell, Rutgers University bushnell@caip.rutgers.edu Bangalore, August 31, 2002

2 Aug 31, '02VDAT'02: Low-Power Design2 Problem Statement Design a digital circuit for minimum transient energy consumption by eliminating hazards

3 Aug 31, '02VDAT'02: Low-Power Design3 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition Ref: Agrawal, et al., Proc. VLSI Design’99

4 Aug 31, '02VDAT'02: Low-Power Design4 Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t 1 --------d t n - t 1 + d t n - t 1 + d t 1 t 2 t 3 t n t n + d t 1 t 2 t 3 t n t n + d time time

5 Aug 31, '02VDAT'02: Low-Power Design5 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

6 Aug 31, '02VDAT'02: Low-Power Design6 Linear Program (LP) Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

7 Aug 31, '02VDAT'02: Low-Power Design7 Limitations of This LP Constraints are written by path enumeration. Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

8 Aug 31, '02VDAT'02: Low-Power Design8 A New LP Model Introduce two new variables per gate output: t i Earliest time of signal transition at gate i. T i Latest time of signal transition at gate i. t 1, T 1 t n, T n...... t i, T i

9 Aug 31, '02VDAT'02: Low-Power Design9 New Linear Program Gate variables d 4..d 12 Buffer Variables d 15..d 29 Corresponding window variables t 4..t 29 and T 4..T 29.

10 Aug 31, '02VDAT'02: Low-Power Design10 Multiple-Input Gate Constraints For Gate 7: T 7 > T 5 + d 7 ; t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ; t 7 < t 6 + d 7 ;

11 Aug 31, '02VDAT'02: Low-Power Design11 Single-Input Gate Constraints T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

12 Aug 31, '02VDAT'02: Low-Power Design12 Overall Delay Constraints T 11 < maxdelay T 12 < maxdelay

13 Aug 31, '02VDAT'02: Low-Power Design13 Validation of the Model For Gate 6 (path-enumeration model): d 1 + d 3 – d 2 < d 6 d 2 – d 3 – d 1 < d 6

14 Aug 31, '02VDAT'02: Low-Power Design14 Validation of the Model For Gate 6 (new model): T 6 > T 2 + d 6 ; t 6 T 6 - t 6 ; T 6 > T 3 + d 6 ; t 6 < t 3 + d 6 ;.. (Ineq. set A)

15 Aug 31, '02VDAT'02: Low-Power Design15 Validation of the Model Buffer Constraints: T 2 = t 2 = d 2 ; T 3 = t 3 = d 3 ; (Ineq. set B) Substituting Ineq. set B in Ineq. set A t 6 – d 2 < d 6..( 1 ) t 6 – d 1 – d 3 < d 6..( 2 ) d 6 < T 6 – d 2..( 3 ) d 6 < T 6 – d 1 – d 3..( 4 )

16 Aug 31, '02VDAT'02: Low-Power Design16 Validation of New Model Adding ineq. ( 1 ) and ( 4 ), and using (A) d 1 + d 3 – d 2 < T 6 – t 6 < d 6 Adding ineq. ( 2 ) and ( 3 ), and using (A) d 2 – d 3 – d 1 < T 6 – t 6 < d 6 These are the same inequalities as for the old path-enumeration model. Similar derivation can be done for maxdelay constraints. Hence the new model constraints are equivalent to the old ones.

17 Aug 31, '02VDAT'02: Low-Power Design17 Why New Model is Superior? Path constraints from old model 4 × 4 × …4 = 4 n Constraints from new model 15 × n = 15n Hence new constraint set is linear in size of circuit.

18 Aug 31, '02VDAT'02: Low-Power Design18 Comparison of Constraints Number of gates in circuit Number of constraints c880 3,611 6.96x10 6

19 Aug 31, '02VDAT'02: Low-Power Design19 Results: Procedure Outline C++ Program AMPL* Power Estimator Combinational circuit netlist Results Constraint-set Optimized delays *Fourer, Gay and Kernighan, AMPL: A Modeling Language for Mathematical Programming, 1993.

20 Aug 31, '02VDAT'02: Low-Power Design20 Results: 1-Bit Adder

21 Aug 31, '02VDAT'02: Low-Power Design21 Estimation of Power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Reference: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ISLPED`97).

22 Aug 31, '02VDAT'02: Low-Power Design22 Original 1-Bit Adder Color codes for number of transitions

23 Aug 31, '02VDAT'02: Low-Power Design23 Optimized 1-Bit Adder Color codes for number of transitions

24 Aug 31, '02VDAT'02: Low-Power Design24 Results: 1-Bit Adder Simulated over all possible vector transitions Average power = optimized/unit delay = 244 / 308 = 0.792 Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 %

25 Aug 31, '02VDAT'02: Low-Power Design25 Results: 4-Bit ALU maxdelayBuffers inserted 75 102 121 150 Power Savings : Peak = 33 %, Average = 21 %

26 Aug 31, '02VDAT'02: Low-Power Design26 Power Dissipation of ALU4 Energy in nanojoules 0 1 2 3 4 5 6 7 0.00.5 1.0 1.5 2.0 microseconds Original ALU delay ~ 3.5ns Minimum energy ALU delay ~ 10ns 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice

27 Aug 31, '02VDAT'02: Low-Power Design27 Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) 17 34 24 48 47 94 43 86 No. of Buffers 95 66 62 34 294 120 366 111 Average 0.72 0.62 0.68 0.40 0.36 0.38 0.36 Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.32 Normalized Power

28 Aug 31, '02VDAT'02: Low-Power Design28 Conclusion Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: Eliminates glitches at all gate outputs, Holds I/O delay within specification, and Combines path-balancing and hazard-filtering to minimize the number of delay buffers. New LP produces results exactly identical to old LP requiring exponential constraint-set. Results show peak power savings up to 40% and average power savings up to 21%.

Download ppt "Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers."

Similar presentations

CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.

CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.
10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.

10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.
1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL 36849 Hillary Grimes & Vishwani D. Agrawal.

1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL Hillary Grimes & Vishwani D. Agrawal.
Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.

Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.
Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL 36849 Nov 19, 20091Agrawal: Low.

Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL Nov 19, 20091Agrawal: Low.
Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.
RTL Hardware Design by P. Chu Chapter 161 Clock and Synchronization.

RTL Hardware Design by P. Chu Chapter 161 Clock and Synchronization.
Partial Implications, etc.

Partial Implications, etc.
Yuanlin Lu Intel Corporation, Folsom, CA 95630 Vishwani D. Agrawal

Yuanlin Lu Intel Corporation, Folsom, CA Vishwani D. Agrawal
May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and.

May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and.
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University,

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University,
Jan. 29, 2002Gaur, et al.: DELTA'021 A New Transitive Closure Algorithm with Application to Redundancy Identification Vivek Gaur Avant! Corp., Fremont,

Jan. 29, 2002Gaur, et al.: DELTA'021 A New Transitive Closure Algorithm with Application to Redundancy Identification Vivek Gaur Avant! Corp., Fremont,
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.
Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal
Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.
Aug 23, ‘021Low-Power Design Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Vishwani D. Agrawal Agere Systems,

Aug 23, ‘021Low-Power Design Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Vishwani D. Agrawal Agere Systems,
Design of Variable Input Delay Gates for Low Dynamic Power Circuits

Design of Variable Input Delay Gates for Low Dynamic Power Circuits
9/23-30/04ELEC 5970-003/6970-0031 ELEC 5970-003/6970-003 (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test.

9/23-30/04ELEC / ELEC / (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test.
May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.

May 14, ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.
August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium.

August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium.

Similar presentations

Ads by Google