1. CS61C L22 CPU Design : Pipelining to Improve Performance II (1) Beamer, Summer 2007 © UCB Scott Beamer, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #22 CPU Design: Pipelining to Improve Performance II 2007-8-1

2. CS61C L22 CPU Design : Pipelining to Improve Performance II (2) Beamer, Summer 2007 © UCB Review: Processor Pipelining (1/2) “Pipeline registers” are added to the datapath/controller to neatly divide the single cycle processor into “pipeline stages”. Optimal Pipeline Each stage is executing part of an instruction each clock cycle. One inst. finishes during each clock cycle. On average, execute far more quickly. What makes this work well? Similarities between instructions allow us to use same stages for all instructions (generally). Each stage takes about the same amount of time as all others: little wasted time.

3. CS61C L22 CPU Design : Pipelining to Improve Performance II (3) Beamer, Summer 2007 © UCB Review: Pipeline (2/2) Pipelining is a BIG IDEA widely used concept What makes it less than perfect? Structural hazards: Conflicts for resources. Suppose we had only one cache?  Need more HW resources Control hazards: Branch instructions effect which instructions come next.  Delayed branch Data hazards: Data flow between instructions.  Forwarding

4. CS61C L22 CPU Design : Pipelining to Improve Performance II (4) Beamer, Summer 2007 © UCB Graphical Pipeline Representation I n s t r. O r d e r Load Add Store Sub Or I$ Time (clock cycles) I$ ALU Reg I$ D$ ALU Reg D$ Reg I$ D$ Reg ALU Reg D$ Reg D$ ALU (In Reg, right half highlight read, left half write) Reg I$

5. CS61C L22 CPU Design : Pipelining to Improve Performance II (5) Beamer, Summer 2007 © UCB Control Hazard: Branching (1/8) Where do we do the compare for the branch? I$ beq Instr 1 Instr 2 Instr 3 Instr 4 ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU Reg D$Reg ALU I$ Reg D$Reg I n s t r. O r d e r Time (clock cycles)

6. CS61C L22 CPU Design : Pipelining to Improve Performance II (6) Beamer, Summer 2007 © UCB Control Hazard: Branching (2/8) We had put branch decision-making hardware in ALU stage therefore two more instructions after the branch will always be fetched, whether or not the branch is taken Desired functionality of a branch if we do not take the branch, don’t waste any time and continue executing normally if we take the branch, don’t execute any instructions after the branch, just go to the desired label

7. CS61C L22 CPU Design : Pipelining to Improve Performance II (7) Beamer, Summer 2007 © UCB Control Hazard: Branching (3/8) Initial Solution: Stall until decision is made insert “no-op” instructions (those that accomplish nothing, just take time) or hold up the fetch of the next instruction (for 2 cycles). Drawback: branches take 3 clock cycles each (assuming comparator is put in ALU stage)

8. CS61C L22 CPU Design : Pipelining to Improve Performance II (8) Beamer, Summer 2007 © UCB Control Hazard: Branching (4/8) Optimization #1: insert special branch comparator in Stage 2 as soon as instruction is decoded (Opcode identifies it as a branch), immediately make a decision and set the new value of the PC Benefit: since branch is complete in Stage 2, only one unnecessary instruction is fetched, so only one no-op is needed Side Note: This means that branches are idle in Stages 3, 4 and 5.

9. CS61C L22 CPU Design : Pipelining to Improve Performance II (9) Beamer, Summer 2007 © UCB Control Hazard: Branching (5/8) Branch comparator moved to Decode stage. I$ beq Instr 1 Instr 2 Instr 3 Instr 4 ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU Reg D$Reg ALU I$ Reg D$Reg I n s t r. O r d e r Time (clock cycles)

10. CS61C L22 CPU Design : Pipelining to Improve Performance II (10) Beamer, Summer 2007 © UCB User inserting no-op instruction Control Hazard: Branching (6a/8) add beq nop ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU Reg D$Reg I$ I n s t r. O r d e r Time (clock cycles) bub ble Impact: 2 clock cycles per branch instruction  slow lw bub ble

11. CS61C L22 CPU Design : Pipelining to Improve Performance II (11) Beamer, Summer 2007 © UCB Controller inserting a single bubble Control Hazard: Branching (6b/8) add beq lw ALU I$ Reg D$Reg ALU I$ Reg D$Reg ALU Reg D$Reg I$ I n s t r. O r d e r Time (clock cycles) bub ble Impact: 2 clock cycles per branch instruction  slow

12. CS61C L22 CPU Design : Pipelining to Improve Performance II (12) Beamer, Summer 2007 © UCB Control Hazard: Branching (7/8) Optimization #2: Redefine branches Old definition: if we take the branch, none of the instructions after the branch get executed by accident New definition: whether or not we take the branch, the single instruction immediately following the branch gets executed (called the branch-delay slot) The term “Delayed Branch” means we always execute inst after branch This optimization is used on the MIPS

13. CS61C L22 CPU Design : Pipelining to Improve Performance II (13) Beamer, Summer 2007 © UCB Control Hazard: Branching (8/8) Notes on Branch-Delay Slot Worst-Case Scenario: can always put a no-op in the branch-delay slot Better Case: can find an instruction preceding the branch which can be placed in the branch-delay slot without affecting flow of the program  re-ordering instructions is a common method of speeding up programs  compiler must be very smart in order to find instructions to do this  usually can find such an instruction at least 50% of the time  Jumps also have a delay slot…

14. CS61C L22 CPU Design : Pipelining to Improve Performance II (14) Beamer, Summer 2007 © UCB Example: Nondelayed vs. Delayed Branch add $1,$2,$3 sub $4, $5,$6 beq $1, $4, Exit or $8, $9,$10 xor $10, $1,$11 Nondelayed Branch add $1,$2,$3 sub $4, $5,$6 beq $1, $4, Exit or $8, $9,$10 xor $10, $1,$11 Delayed Branch Exit:

15. CS61C L22 CPU Design : Pipelining to Improve Performance II (15) Beamer, Summer 2007 © UCB Out-of-Order Laundry: Don’t Wait A depends on D; rest continue; need more resources to allow out-of-order TaskOrderTaskOrder 12 2 AM 6 PM 7 8 9 10 11 1 Time B C D A 30 E F bubble

16. CS61C L22 CPU Design : Pipelining to Improve Performance II (16) Beamer, Summer 2007 © UCB Superscalar Laundry: Parallel per stage More resources, HW to match mix of parallel tasks? TaskOrderTaskOrder 12 2 AM 6 PM 7 8 9 10 11 1 Time B C D A E F (light clothing) (dark clothing) (very dirty clothing) (light clothing) (dark clothing) (very dirty clothing) 30

17. CS61C L22 CPU Design : Pipelining to Improve Performance II (17) Beamer, Summer 2007 © UCB Superscalar Laundry: Mismatch Mix Task mix underutilizes extra resources TaskOrderTaskOrder 12 2 AM 6 PM 7 8 9 10 11 1 Time 30 (light clothing) (dark clothing) (light clothing) A B D C

18. CS61C L22 CPU Design : Pipelining to Improve Performance II (18) Beamer, Summer 2007 © UCB Real-world pipelining problem You’re the manager of a HUGE assembly plant to build computers. Box Problem: need to run 2 hr test before done..help! Main pipeline 10 minutes/ pipeline stage 60 stages Latency: 10hr

19. CS61C L22 CPU Design : Pipelining to Improve Performance II (19) Beamer, Summer 2007 © UCB Real-world pipelining problem solution 1 You remember: “a pipeline frequency is limited by its slowest stage”, so… Box Problem: need to run 2 hr test before done..help! Main pipeline 10 minutes/ pipeline stage 60 stages Latency: 10hr 2hours/ 120hr

20. CS61C L22 CPU Design : Pipelining to Improve Performance II (20) Beamer, Summer 2007 © UCB Real-world pipelining problem solution 2 Create a sub-pipeline! Main pipeline 10 minutes/ pipeline stage 60 stages Box 2hr test (12 CPUs in this pipeline)

21. CS61C L22 CPU Design : Pipelining to Improve Performance II (21) Beamer, Summer 2007 © UCB Peer Instruction (1/2) Assume 1 instr/clock, delayed branch, 5 stage pipeline, forwarding, interlock on unresolved load hazards (after 10 3 loops, so pipeline full) Loop:lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) addiu $s1, $s1, -4 bne $s1, $zero, Loop nop How many pipeline stages (clock cycles) per loop iteration to execute this code? 1 2 3 4 5 6 7 8 9 10

22. CS61C L22 CPU Design : Pipelining to Improve Performance II (22) Beamer, Summer 2007 © UCB Peer Instruction Answer (1/2) Assume 1 instr/clock, delayed branch, 5 stage pipeline, forwarding, interlock on unresolved load hazards. 10 3 iterations, so pipeline full. Loop:lw$t0, 0($s1) addu$t0, $t0, $s2 sw$t0, 0($s1) addiu$s1, $s1, -4 bne$s1, $zero, Loop nop How many pipeline stages (clock cycles) per loop iteration to execute this code? 1. 2. (data hazard so stall) 3. 4. 5. 7. (delayed branch so exec. nop) 8. 1 2 3 4 5 6 7 8 9 10 6. (!= in DCD)

23. CS61C L22 CPU Design : Pipelining to Improve Performance II (23) Beamer, Summer 2007 © UCB Peer Instruction (2/2) Assume 1 instr/clock, delayed branch, 5 stage pipeline, forwarding, interlock on unresolved load hazards (after 10 3 loops, so pipeline full). Rewrite this code to reduce pipeline stages (clock cycles) per loop to as few as possible. Loop:lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) addiu $s1, $s1, -4 bne $s1, $zero, Loop nop How many pipeline stages (clock cycles) per loop iteration to execute this code? 1 2 3 4 5 6 7 8 9 10

24. CS61C L22 CPU Design : Pipelining to Improve Performance II (24) Beamer, Summer 2007 © UCB Peer Instruction (2/2) How long to execute? How many pipeline stages (clock cycles) per loop iteration to execute your revised code? (assume pipeline is full) Rewrite this code to reduce clock cycles per loop to as few as possible: Loop:lw$t0, 0($s1) addiu$s1, $s1, -4 addu$t0, $t0, $s2 bne$s1, $zero, Loop sw$t0, +4($s1) (no hazard since extra cycle) 1. 3. 4. 5. 2. (modified sw to put past addiu) 1 2 3 4 5 6 7 8 9 10

25. CS61C L22 CPU Design : Pipelining to Improve Performance II (25) Beamer, Summer 2007 © UCB “And in Early Conclusion..” Pipeline challenge is hazards Forwarding helps w/many data hazards Delayed branch helps with control hazard in 5 stage pipeline Load delay slot / interlock necessary More aggressive performance: Superscalar Out-of-order execution

26. CS61C L22 CPU Design : Pipelining to Improve Performance II (26) Beamer, Summer 2007 © UCB Administrivia Assignments HW7 due 8/2 Proj3 due 8/5 Midterm Regrades due Today Logisim in lab is now 2.1.6 java -jar ~cs61c/bin/logisim Valerie’s OH on Thursday moved to 10- 11 for this week

27. CS61C L22 CPU Design : Pipelining to Improve Performance II (27) Beamer, Summer 2007 © UCB Why Doesn’t It Work? DO NOT MESS WITH THE CLOCK Crafty veterans may do it very rarely and carefully Doing so will cause unpredictable and hard to track errors Following slides are from CS 150 Lecture by Prof. Katz

28. CS61C L22 CPU Design : Pipelining to Improve Performance II (28) Beamer, Summer 2007 © UCB IN Q0 Q1 CLK 100 Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) CLK IN Q0Q1 DQDQOUT

29. CS61C L22 CPU Design : Pipelining to Improve Performance II (29) Beamer, Summer 2007 © UCB IN Q0 Q1 CLK 100 Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) CLK IN Q0Q1 DQDQOUT Delay Clk1

30. CS61C L22 CPU Design : Pipelining to Improve Performance II (30) Beamer, Summer 2007 © UCB original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 CLK1 is a delayed version of CLK In Q0 Q1 CLK CLK1 100 Clock Skew The problem Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay) Effect of skew on cascaded flip-flops:

31. CS61C L22 CPU Design : Pipelining to Improve Performance II (31) Beamer, Summer 2007 © UCB Why Gating of Clocks is Bad! Reg Clk LD Reg Clk LD GOOD BAD Do NOT Mess With Clock Signals! gatedClK

32. CS61C L22 CPU Design : Pipelining to Improve Performance II (32) Beamer, Summer 2007 © UCB Why Gating of Clocks is Bad! Do NOT Mess With Clock Signals! Clk LD gatedClk LD generated by FSM shortly after rising edge of CLK Runt pulse plays HAVOC with register internals! Clk LDn gatedClk NASTY HACK: delay LD through negative edge triggered FF to ensure that it won’t change during next positive edge event Clk skew PLUS LD delayed by half clock cycle … What is the effect on your register transfers?

33. CS61C L22 CPU Design : Pipelining to Improve Performance II (33) Beamer, Summer 2007 © UCB The Big Picture Processor (active) Computer Control (“brain”) Datapath (“brawn”) Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk, Network

34. CS61C L22 CPU Design : Pipelining to Improve Performance II (34) Beamer, Summer 2007 © UCB Memory Hierarchy Processor holds data in register file (~100 Bytes) Registers accessed on nanosecond timescale Memory (we’ll call “main memory”) More capacity than registers (~Gbytes) Access time ~50-100 ns Hundreds of clock cycles per memory access?! Disk HUGE capacity (virtually limitless) VERY slow: runs ~milliseconds Storage in computer systems:

35. CS61C L22 CPU Design : Pipelining to Improve Performance II (35) Beamer, Summer 2007 © UCB Motivation: Why We Use Caches (written $) µProc 60%/yr. DRAM 7%/yr. 1 10 100 1000 19801981198319841985198619871988 1989 1990 1991199219931994199519961997199819992000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance 1989 first Intel CPU with cache on chip 1998 Pentium III has two levels of cache on chip

36. CS61C L22 CPU Design : Pipelining to Improve Performance II (36) Beamer, Summer 2007 © UCB Memory Caching Mismatch between processor and memory speeds leads us to add a new level: a memory cache Implemented with same IC processing technology as the CPU (usually integrated on same chip): faster but more expensive than DRAM memory. Cache is a copy of a subset of main memory. Most processors have separate caches for instructions and data.

37. CS61C L22 CPU Design : Pipelining to Improve Performance II (37) Beamer, Summer 2007 © UCB Memory Hierarchy Processor Size of memory at each level Increasing Distance from Proc., Decreasing speed Level 1 Level 2 Level n Level 3... Higher Lower Levels in memory hierarchy As we move to deeper levels the latency goes up and price per bit goes down.

38. CS61C L22 CPU Design : Pipelining to Improve Performance II (38) Beamer, Summer 2007 © UCB Memory Hierarchy If level closer to Processor, it is: smaller faster subset of lower levels (contains most recently used data) Lowest Level (usually disk) contains all available data (or does it go beyond the disk?) Memory Hierarchy presents the processor with the illusion of a very large very fast memory.