1. Puneet Sharma and Puneet Gupta Prof. Andrew B. Kahng Prof. Dennis Sylvester System-Level Living Roadmap Annual Review, Sept. 2004 Basic Ideas Gate-length biasing implies increasing the gate-length by 5%-10%. Impact of gate-length biasing: Leakage reduces exponentially Delay increases linearly Impact on leakage variability: Gate-Length Biasing A Highly Manufacturable Approach To Leakage Control Device Numer Gate Length (nm) PMOSNMOS UnbiasedBiasedDiff.UnbiasedBiasedDiff. 1125132+7126132+6 2124126+2126129+3 3124126+2126129+3 4121127+6124130+6 5121127+6122128+6 6122128+6122128+6 7125131+6122131+7 DOF(µm)ELAT(%) for 130nmELAT(%) for 136nm 0.097.667.71 0.336.977.04 0.505.986.23 0.674.675.02 1.002.062.71 Gate-Length Leakage Gate-Length Variability Biasing Leakage Variability Spice Mode l Spice Netlists Biased Gate-Length Biased Gate-Length Granularity Characterize and augment standard cell library such that each master has a biased gate-length variant Characterize and augment standard cell library such that each master has a biased gate-length variant Extended Standard Cell Library Extended Standard Cell Library Circuit Netlist Modified Netlist Dynamic + Leakage Power Estimate Dynamic + Leakage Power Estimate Introduction With process scaling, leakage power reduction has become one of the most important design goals. In this research, we study the efficacy and feasibility of using a marginally increased gate- length for leakage power reduction. Delay increases linearly and leakage decreases exponentially as gate-length increases. We utilize this fact to propose the use of an increased gate-length for non-critical devices in a circuit. Application of this technique results in reduced leakage and leakage variability while having very small impact on circuit performance. Unlike the multi-V t approach, which is highly effective and used in practice, the proposed approach does not require additional process steps and can be applied anytime during the design cycle. Device Biasing Which devices to bias? Gate-length biasing reduces leakage and its variability, however, with a delay penalty. Solution: Selectively bias devices that are non-critical to circuit performance  Reduction of leakage and its variability with no or very small delay penalty How much to bias? Constrained to less than 10% to preserve pin- and layout- compatibility.  Approach applicable as a post-layout/post-RET step Methodology Overview Leakage Optimizer Uses slower, low-leakage cells in non-critical paths Uses faster, high-leakage cells in critical paths Leakage Optimizer Uses slower, low-leakage cells in non-critical paths Uses faster, high-leakage cells in critical paths Methodology Details Circuit delay penalty of less than 2.5% Results: Leakage Variability Leakage variability reduction: 39%-54% Leakage distribution for alu128 Percentage reduction in leakage spread Ongoing Work Extend to sequential test cases Allow devices in a cell to have different biasing, and have cell variants with different sets of timing arcs slowed down Rise & fall transitions not both critical  bias devices that govern the non-critical transition Timing arcs of a cell not all critical  bias devices to make non-critical arcs slow and reduce leakage Initial results: Additional 2%-5% leakage reduction Significant leakage variability reduction Disadvantages: Increased cell library and GDSII size Evaluate at future technology nodes Results: Manufacturability Results: Leakage Leakage power reduction Single Vt designs: 14-26% Dual Vt designs: 4-15% High correlation between drawn and printed gate-length Printed and drawn gate- lengths of devices in AND2X6. Unbiased gate-length is 130nm; biased gate-length is 136nm. Tools: Mentor Calibre for OPC; Printimage for litho simulation Process window improves with gate-length CD tolerance: 13nm ELAT: Exposure latitude DOF: Depth of Focus Tools: KLA-Tencor Prolith Results generated by 2000 Monte-Carlo simulations  WID =  DTD =3.33nm. Variations assumed to be Gaussian with no correlation. Granularity: Freedom to assign different biased gate-lengths to different devices. We consider three options: Technology level: All devices in the library have the same biased gate- length. Cell level: All devices in a cell have the same biased gate-length. Devices in different cells may have different biased gate-lengths. Device level: All devices are free to have an independent biased gate- length. Our approach: For each cell, NMOS devices have one biased gate-length and PMOS devices have an independent biased gate-length. Devices In different cells have independent biased gate-lengths. Leakage optimizer: Simple TILOS like sizer; starts with all fastest cells, replaces cells that have slack with slower, low- leakage variants.