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Evaluation of Placement Techniques for DNA Probe Array Layout Andrew B. Kahng 1 Ion I. Mandoiu 2 Sherief Reda 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department,

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Presentation on theme: "Evaluation of Placement Techniques for DNA Probe Array Layout Andrew B. Kahng 1 Ion I. Mandoiu 2 Sherief Reda 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department,"— Presentation transcript:

1 Evaluation of Placement Techniques for DNA Probe Array Layout Andrew B. Kahng 1 Ion I. Mandoiu 2 Sherief Reda 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University of California at San Diego (2) CSE Department, University of Connecticut (3) CS Department, Georgia State University

2 Introduction to DNA microarrays and border minimization challenges Outline Partitioning-based probe placement Comparison of probe placement heuristics Quantified sub-optimality of placement Conclusions and future research directions Previous probe placement algorithm

3 Introduction to DNA Probe Arrays DNA Arrays are composed of probes where each probe is a sequence of 25 nucleotides Images courtesy of Affymetrix. Optical scanning Laser activation Tagged fragments flushed over array

4 Probe Synthesis array probes A 3 X 3 array CGACACG ACAC ACGAGAG CG AGAGC Nucleotide Deposition Sequence ACG A  Mask 1 A A A A A

5 Probe Synthesis array probes CGCGACACG ACAC ACGACGAGAG CGCG AGAGC Nucleotide Deposition Sequence ACG C C C C C C A A A A A A 3 X 3 array C  Mask 2

6 Probe Synthesis array probes CGCGACG ACGAGAG CGCG AGAGC Nucleotide Deposition Sequence ACG C C C C C C A A A A A G GG G G G A Nucleotide Deposition Sequence defines the order of nucleotide deposition A Probe Embedding specifies the steps it uses in the sequence to get placed A 3 X 3 array G  Mask 3

7 Border Minimization Challenges Lamp Mask Array Problem: Diffraction, internal reflection, scattering, internal illumination Occurs at sites near to intentionally exposed sites Reduce Border  Increase yield  Reduce cost Design objective: Minimize the border Intentionally exposed sites Unwanted illumination Border

8 Border Reduction with Probe Placement Probe Placement  Similar probes should be placed close together Deposition Sequence A A C C G G T T C T T A Probes C T C T C T T A Border = 8 C T C T T A C T T T A C Border = 4 Optimize

9 Border Reduction in Probe Embedding Synchronous embedding: deposit one nucleotide in each group of “ACGT” Probe Embedding Asynchronous embedding: no restriction Deposition Sequence A A C C G G T T C T T A Probes C T T A Border = 4 C T T A C TT A Border = 2

10 Basic DNA Array Design Flow Probe Selection Design of Test Probes Probe Placement Probe Embedding DNA Array Logic Synthesis BIST and DFT Placement Routing VLSI Chip Physical Design Probe Placement Probe Embedding Probe Selection Design of Test Probes Logic Synthesis BIST and DFT Physic al Design Routing Placement Analogy Lithography

11 DNA Microarrays Physical Design Problem Placement of probes in n x n sites Give: n 2 probes Total border cost Find: Embedding of the probes Minimize:

12 Introduction to DNA microarrays and border minimization challenges Outline Partitioning-based probe placement Comparison of probe placement heuristics Quantified sub-optimality of placement Conclusions and future research directions Previous probe placement algorithm

13 Previous Work Border minimization was first introduced by Feldman and Pevzner. “Gray Code masks for sequencing by hybridization,” Genomics, 1994, pp. 233-235 Work by Hannenhalli et al. gave heuristics for the placement problem by using a TSP formulation. Kahng et al. “Border length minimization in DNA Array Design,” WABI02, suggested constructive methods for placement and embedding Kahng et al. “Engineering a Scalable Placement Heuristic for DNA Probe Arrays,” RECOMB03, suggested scalable placement improvement and embedding techniques

14 1-D Probe Placement (TSP) How to place the 1-D ordering of probes onto the 2-D chip? Probe 1Probe 2Probe 3Probe 4 A C G A C G C T T T T C A C G A T C C C T A T C A C G A C G Probe 1 A C G A T C Probe 3Probe 4 C C T A T C Probe 2 C T T T T C Hamming Distance (P 1, P 2 ) = number of nucleotides which are different from its counterpart = border (synchronous embedding) Hamming Distance =4

15 Placement By Threading Thread on the chip 1 2 3 4 A C G A C G Probe 1 A C G A T C Probe 2Probe 3 C C T A T C Probe 4 C T T T T C Optimized Edge Not Optimized Edge

16 Row-Epitaxial Placement For each site position (i, j): Find the best probe which minimize border (i, j) Move the best probe to (i, j) and lock it in this position Switch

17 Introduction to DNA microarrays and border minimization challenges Outline Partitioning-based probe placement Comparison of probe placement heuristics Quantified sub-optimality of placement Conclusions and future research directions Previous probe placement algorithm

18 Basic DNA Array Design Flow Partitioning Placement Question: Shall we use partitioning in probe placement? Probe Selection Design of Test Probes Probe Placement Probe Embedding DNA Array Logic Synthesis BIST and DFT Placement Routing VLSI Chip Physical Design Probe Placement Probe Embedding Probe Selection Design of Test Probes Logic Synthesis BIST and DFT Physic al Design Routing Placement Analogy Lithography

19 Single Nucleotide Placement AAAAAAAA AAAAAAAA C C C C C C C C C C C C C C C C G G T T G G T T G G T T G G T T G G T T G G T T G G T T G G T T Row-Epitaxial Placement Border = 48 AAAA AAAA AAAA AAAA C C C C C C C C C C C C C C C C G G T T G G T T G G T T G G T T G G T T G G T T G G T T G G T T Partitioning Based Placement Border = 32 Can partitioning based placement achieve improvement for 25-nucleotide probes?

20 Partitioning Based Placement Randomly choose a probe as seed 1. Choose a probe as seed 2 which has the largest Hamming distance with seed 1. Choose a probe as seed 3 which has the largest total Hamming distance with seed 1 and seed 2. Choose a probe as seed 4 which has the largest total Hamming distance with seed 1, seed 2 and seed 3.

21 Partitioning Based Placement Level 1 Partition Level 2 Partition Row epitaxial one by one “Border aware”

22 Introduction to DNA microarrays and border minimization challenges Outline Partitioning-based probe placement Comparison of probe placement heuristics Quantified sub-optimality of placement Conclusions and future research directions Previous probe placement algorithm

23 2-D Gray code Placement n=2 n=4 For synchronous embedding, Border = 2 for any two neighbor probes. C G A T A C T C C C G C T G A G G G C G A A T A T T A T C A G A G T C T

24 Scaling Construction n x n real chip Ratio=<1Solution quality scale well new border 4(old border) A AA A CC A GG A TT A GA A TC A AG A CT CA A GC TG A AT A CA A GC A TG A AT Four isomorphic copies with the same border

25 Introduction to DNA microarrays and border minimization challenges Outline Partitioning-based probe placement Comparison of probe placement heuristics Quantified sub-optimality of placement Conclusions and future research directions Previous probe placement algorithm

26 Experiments Setup Chip size range: between 100x100 and 500x500 Randomly generated Type of instances 2-D Gray code Scaled / suboptimality test cases Synchronous Embedding methods Asynchronous Total border cost Quality measure Gap from lower bound Normalized cost CPU All tests are run on Xeon 2.4 GHz CPU.

27 Comparison of Synchronous Placement Results Chip size Borders Chip size CPU TSP + ThreadingRow Epitaxial Partitioning Based (Level=2) Chip size Gap from lower bound Chip size Normalized cost Compared with row epitaxial, new method reduce the border cost by 3.7% and is 3 times faster.

28 Results on 2-D Gray code Test cases Chip size Borders TSP + Threading Row Epitaxial Recursive Partitioning Chip size Gap from Optimal solution 5.6%

29 Suboptimality Experiments Results Chip size Borders Row Epitaxial Partitioning Based (Level=2) Chip size Scaling ratio 2.5%

30 Placement Polishing Using Re-Embedding Use polishing algorithm to re-embed each probe with respect to its neighbors Perform polishing one by one Deposition Sequence A A C C G G T T T C C G Probes A C C T C A C G Border = 8 Border = 4

31 Comparison of Asynchronous Placement Results Chip size Borders Chip size CPU TSP + ThreadingRow Epitaxial Partitioning Based (Level=2) Chip size Gap from lower bound Chip size Normalized cost Compared with row epitaxial, new method reduce the border cost by 4% and is 2.65 times faster.

32 Introduction to DNA microarrays and border minimization challenges Outline Partitioning-based probe placement Comparison of probe placement heuristics Quantified sub-optimality of placement Conclusions and future research directions Previous probe placement algorithm

33 Conclusions We draw a fertile analogue between DNA array and VLSI Design Automation We propose a new recursive partitioning-based placement algorithm and a new embedding algorithm which achieves 4% improvement We study and quantify the performance of existing and newly proposed algorithms on benchmarks with known optimal cost as well as scaling suboptimality experiments

34 Open Research Directions Stronger placement operators leading to further reduction in the border cost. Future work also covers next generation chips 10k × 10k. Add flow-awareness to each optimization step and introduce feedback loops. Add the pools of probes taken from probe selection tool.

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