1. Aleksandra Tešanović Low Power/Energy Scheduling for Real-Time Systems Aleksandra Tešanović Real-Time Systems Laboratory Department of Computer and Information Science Linköpings universitet Sweden

2. 2 Aleksandra Tešanović Talk Outline Variable Voltage Processors Static Voltage Scheduling Dynamic Voltage Scheduling

3. 3 Aleksandra Tešanović Power Delay Trade-off lowerlowerlower supply voltage => lower power/energy consumption lowerhigherlower power/energy consumption => higher circuit delay/execution time

4. 4 Aleksandra Tešanović Variable Voltage Processors variable voltage generated by DC-DC switching regulators –DC-DC switching regulators with fast transition times –time and power overhead of switching is negligible ROM Vdd CLK CPU Vdd CLK RAM Vdd CLK Vdd control DC-DC converter & VCO

5. 5 Aleksandra Tešanović Variable Voltage Processors voltage can be changed by the instructions in applications or operating system clock adjusted to the voltage high supply voltage –high execution speed -> tasks with severe real-time constraints low supply voltage –low execution speed -> tasks with loose real-time constraints

6. 6 Aleksandra Tešanović Basic Idea 0 5 10 15 20 25 Time(seconds) 5.0 2 0 5 10 15 20 25 Time(seconds) 5.0 2 32.5 J 25 J 2.5 2 4.0 2 Single supply fitting the execution time minimizes energy consumption Energy consumption (  V DD ) 0 5 10 15 20 25 Time(seconds) 5.0 2 40 J Time constraint 1 billion cycles 750 million cycles 250 million cycles 1 billion cycles Lema1&2

7. 7 Aleksandra Tešanović Load Capacitance 0 5 10 15 20 25 Time(seconds) 5.0 2 0 5 10 15 20 25 Time(seconds) 5.0 2 25 J 2.5 2 4.0 2 Energy consumption (  V DD ) 750 million cycles 250 million cycles 1 billion cycles Task1 Task2 LC 1 2.0 F X 1 250 million cycles LC 2 0.5 F X 2 750 million cycles Capacitive load

8. 8 Aleksandra Tešanović Challenges schedulingvoltage Effective scheduling techniques that treat voltage as variable to be determined, in addition to conventional task scheduling and allocation. real-time application consists of two or more tasks variable-voltage processor uses few discrete voltages load capacitance is different for each task tasks end earlier then in worst-case execution cycles scheduler can’t execute tasks before their arrival time. Static Dynamic

9. 9 Aleksandra Tešanović Basic Theorems before energy consumption is not minimized. LEMA1 If a processor completes to process a program before deadline (T), the energy consumption is not minimized. LEMA1 LEMA2 single supply voltage completes the program V(=V ideal ) If a processor uses a single supply voltage (V) and completes the program just at a deadline T, than V(=V ideal ) is an unique supply voltage which minimizes energy consumption for the processing. THEOREM1 voltage scheduling with at most two voltages minimizes the energy consumption If a processor can use only a small number of discretely variable voltages, the voltage scheduling with at most two voltages minimizes the energy consumption under any time constraint. THEOREM2 If a processor can use only a small number of discretely variable voltages, the two voltages which minimize the energy consumption under time constraint T are immediate neighbors to the ideal voltage.

10. 10 Aleksandra Tešanović Generalized Theorems LEMA3 If a processor uses continuously variable voltage, the voltage scheduling which assigns a single voltage for each task minimizes energy consumption for a given program under a time constraint. THEOREM3 If a processor can use only a small number of discretely variable voltages and LC j are different from each other, the voltage scheduling with at most two voltages for each task minimizes the energy consumption under a time constraint.

11. 11 Aleksandra Tešanović Voltage Scheduling Techniques static voltage scheduling –target systems –ILP problem formulation dynamic voltage scheduling –target systems –algorithms (SD and DD)

12. 12 Aleksandra Tešanović Static Scheduling - Target System hard real-time system can vary its supply voltage dynamically uses only one supply voltage at a time few discrete voltages adaptive clock scheme worst-case execution cycles can be estimated statically no power overhead due to DC-DC switches no time overhead due to voltage and clock changing

13. 13 Aleksandra Tešanović Static Scheduling - Formulation N - number of tasks task j =(X j,C j ) - the jth task X j - number of cycles of the jth task C j - average capacitve load for jth task L - number of variable voltages Mode i =(V i,F i ) - processor’s execution mode V i - ith voltage F i - clock frequency with V i T - time constraint x ij - number of cycles of task j executed with V i VOLTAGE SCHEDULING PROBLEM … for the given {task j } and {mode i }, find x ij, that minimizes E and satisfies time constraint T. minimize subject to 2

14. 14 Aleksandra Tešanović Static Scheduling - Experimental Results high number of variable voltages => power reduction suitable voltage for the time constraint => significant power reduction tasks with lower capacitance, assigned higher voltage => 30% reduction of energy consumption

15. 15 Aleksandra Tešanović Dynamic Scheduling - Notation TASK PARAMETERS a i - arrival time O i - worst-case execution time d i - deadline s i - execution start time e i - execution completion time L i - remaining time : L i =d i -e i ENERGY CONSUMPTION PARAMETERS X i - worst case execution cycle Fi - clock frequency with J i V i - supply voltage when J i executes C i - average capacitive load E i - worst-case energy consumption O i =X i /F i E i =C i X i V i 2 a i s i e i d i TASK J i PROCESSOR PARAMETERS (v j,f j ) - processor mode m= (v j,f j ) - number of processor modes V max =max(v i ) - largest supply voltage OiOi LiLi

16. 16 Aleksandra Tešanović Dynamic Scheduling Algorithms SD algorithm –arrival times of tasks known DD algorithm –arrival times of tasks unknown target systems –real-time system (RTOS + applications) –application programs divided in tasks –task can vary supply voltage –preemptive tasks

17. 17 Aleksandra Tešanović Algorithm Steps CPU time allocation –all tasks execute on V max –execution cycle = worst case end-time prediction –time slot’s end time for next executed task is predicted start-time assignment –time slot’s start-time is determined –time slot can be lengthened if the previous task finishes earlier

18. 18 Aleksandra Tešanović Experimental Results SD algorithm –better results than the normal case –looser deadline constraints => better energy reduction DD algorithm –better results than the normal case –power consumption independent of deadline constraints

19. 19 Aleksandra Tešanović Summary