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May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.

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Presentation on theme: "May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani."— Presentation transcript:

1 May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Presented at the IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, May 13-15, 2009

2 May 14, 2009 2ISVLSI 09 Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat =P tran + P sc + P stat

3 May 14, 2009 3ISVLSI 09 Power Per Transition V DD Ground CLCL R R Dynamic Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

4 May 14, 2009 4ISVLSI 09 Number of Transitions

5 May 14, 2009 5ISVLSI 09 Outline Motivation and Problem Statement Motivation and Problem Statement Background Background Contributions: Contributions: A New Dynamic Power Analysis Algorithm  Bounded Delays and Ambiguity Intervals  Maximum Transitions  Minimum Transitions  Simulation and Power Estimation  Experimental Results and Observations Conclusion Conclusion

6 May 14, 2009 6ISVLSI 09 Problem Statement and Motivation Problem - Estimate dynamic power consumed in a CMOS circuit for: Problem - Estimate dynamic power consumed in a CMOS circuit for: A set of input vectors A set of input vectors Delays subjected to process variation (typical in nanoscale technologies) Delays subjected to process variation (typical in nanoscale technologies) Challenge - Existing method, Monte Carlo simulation, is expensive. Challenge - Existing method, Monte Carlo simulation, is expensive. Find a lower cost solution. Find a lower cost solution.

7 May 14, 2009 7ISVLSI 09 Background Bounded delay model is used to address process variations in logic level simulation and timing analysis. See references in the paper. Bounded delay model is used to address process variations in logic level simulation and timing analysis. See references in the paper. We model delay uncertainties by assigning each gate lower and upper bounds on its delay. These are known as min–max delays. We model delay uncertainties by assigning each gate lower and upper bounds on its delay. These are known as min–max delays. The bounds are obtained by adding specified process-related variation to the nominal gate delay for the technology. The bounds are obtained by adding specified process-related variation to the nominal gate delay for the technology.

8 References J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s Thesis, Auburn University, December 2008. J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s Thesis, Auburn University, December 2008. J J. D. Alexander and V. D. Agrawal, “Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation,” Proc. 41 st IEEE Southeastern Symp. System Theory, March 2009, pp. 107-112. Paper describes simulation algorithm and results. J. D. Alexander and V. D. Agrawal, “Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation,” Proc. 41 st IEEE Southeastern Symp. System Theory, March 2009, pp. 107-112. Paper describes simulation algorithm and results. This paper: Theoretical foundation – theorems on ambiguity propagation and maximum and minimum transitions – make the fast zero-delay analysis possible. This paper: Theoretical foundation – theorems on ambiguity propagation and maximum and minimum transitions – make the fast zero-delay analysis possible. May 14, 2009 8ISVLSI 09

9 May 14, 2009 9ISVLSI 09 Ambiguity Intervals EA is the earliest arrival time LS is the latest stabilization time IV is the initial signal value FV is the final signal value IVFV LSEA IVFV EALS EAdvLSdv EAsv=-∞LSsv=∞ EAsvLSsv EAdv=-∞LSdv=∞

10 May 14, 2009 10ISVLSI 09 Propagating Ambiguity Intervals through Gates The ambiguity interval (EA,LS) for a gate output is determined by: Ambiguity intervals of input signals. Pre-transition and Post-transition steady-state values. Min-Max gate delays. (mindel, maxdel)‏

11 May 14, 2009 11ISVLSI 09 Representative Formulae To evaluate the output of a gate, we analyze inputs i: To evaluate the output of a gate, we analyze inputs i:

12 May 14, 2009 12ISVLSI 09 Theorem 1: Propagating Ambiguity Intervals Ambiguity interval at a gate output is: Ambiguity interval at a gate output is: where the inertial delay of the gate is bounded as (mindel, maxdel). where the inertial delay of the gate is bounded as (mindel, maxdel).

13 May 14, 2009 13ISVLSI 09 Finding Number of Transitions 2 1,3 3 14 5 8 10 12 (mindel, maxdel)‏ 7 10 12 14 5 17 EA LS 3 14 EA LS [0,4] [0,2] 6 17 EA LS [mintran,maxtran] where mintran is the minimum number of transitions and maxtran the maximum number of transitions.

14 May 14, 2009 14ISVLSI 09 Theorem 2: Maximum Transitions First upper bound: We calculate the maximum transitions (Nd) that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV,FV) output values. First upper bound: We calculate the maximum transitions (Nd) that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV,FV) output values. Second upper bound: We take the sum of the input transitions (N) as the output cannot exceed this. We modify this by : Second upper bound: We take the sum of the input transitions (N) as the output cannot exceed this. We modify this by : N = N – k N = N – k where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs. The maximum number of transitions is lower of the two upper bounds: The maximum number of transitions is lower of the two upper bounds: maxtran = min (Nd, N) maxtran = min (Nd, N)

15 May 14, 2009 15ISVLSI 09 Examples of maxtran (k = 0) ‏ Nd = ∞ N = 8 maxtran=min (Nd, N) = 8 Nd = 6 N = 8 maxtran=min (Nd, N) = 6

16 May 14, 2009 16ISVLSI 09 Example: maxtran With Non-Zero k EAsv = - ∞ EAdv LSdv = ∞ LSsv EAsv = - ∞ LSdv = ∞ EAdvLSsv EALS [n1 = 6] [n2 = 4] [n1 + n2 – k = 8 ], where k = 2 [ 6 ] [ 4 ] [ 6 + 4 – 2 = 8 ]

17 May 14, 2009 17ISVLSI 09 Theorem 3: Minimum Transitions First lower bound (Ns): Based on steady state values, i.e., 0  0, 1  1 as no transition and 0  1, 1  0 as a single transition. First lower bound (Ns): Based on steady state values, i.e., 0  0, 1  1 as no transition and 0  1, 1  0 as a single transition. Second lower bound (Ndet): The minimum number of transitions that can occur in the output ambiguity region is the number of deterministic signal changes that occur within the ambiguity region and such that signal changes are spaced at time intervals greater than or equal to the inertial delay of the gate. Second lower bound (Ndet): The minimum number of transitions that can occur in the output ambiguity region is the number of deterministic signal changes that occur within the ambiguity region and such that signal changes are spaced at time intervals greater than or equal to the inertial delay of the gate. The minimum number of transitions is the higher of the two lower bounds: The minimum number of transitions is the higher of the two lower bounds: mintran = max (Ns, Ndet) mintran = max (Ns, Ndet)

18 May 14, 2009 18ISVLSI 09 Example: mintran There will always be a hazard in the output as long as There will always be a hazard in the output as long as (EAsv – LSdv) ≥ maxdel Thus in this case the mintran is not 0 as per the steady state condition, but is 2. Thus in this case the mintran is not 0 as per the steady state condition, but is 2. d EAsv = - ∞ EAdv LSsv = ∞ LSdv EAdv = - ∞ LSdv = ∞ EAsvLSsv EALS (mindel, maxdel)‏

19 May 14, 2009 19ISVLSI 09 Power Analysis Algorithm maxdel, mindel = nominal delay ± Δ% maxdel, mindel = nominal delay ± Δ% Three linear-time passes for each input vector: Three linear-time passes for each input vector:  First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals.  Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and bounded gate delays.  Third pass: determines upper and lower bounds, maxtran and mintran, for all gates from the above information.

20 May 14, 2009 20ISVLSI 09 Simulation Setup Simulation Setup Standard gate delay 100 ps. Standard gate delay 100 ps. Wire-load model used; gate proportional to fan–out. Wire-load model used; gate proportional to fan–out. The power distribution determined for 1000 random vectors with a vector period of 10000 ps. The power distribution determined for 1000 random vectors with a vector period of 10000 ps. For each vector pair, 1000 sample circuits were simulated. For each vector pair, 1000 sample circuits were simulated.

21 Maximum Power Monte Carlo Simulation vs. Min-Max analysis for circuit C880. 100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). Monte Carlo Simulation vs. Min-Max analysis for circuit C880. 100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). May 14, 2009 ISVLSI 0921 R 2 is coefficient of determination, equals 1.0 for ideal fit.

22 Minimum Power May 14, 2009 ISVLSI 09 22 R 2 is coefficient of determination, equals 1.0 for ideal fit.

23 Average Power R 2 is coefficient of determination, equals 1.0 for ideal fit. May 14, 2009 23ISVLSI 09

24 C880: Monte Carlo vs. Bounded Delay Analysis May 14, 2009 ISVLSI 0924 Monte Carlo SimulationBounded Delay Analysis Min Power (mW) Max Power (mW) CPU Time (secs) Min Power (mW) Max Power (mW) CPU Time (secs) 1.4211.59262.71.3511.890.3 1000 Random Vectors, 1000 Sample Circuits

25 May 14, 2009 25 ISVLSI 09 C2670: Effect of Inertial Delay Transition Statistics for high activity gate 1407 in c2670 for a random vector pair. Histograms obtained from Monte Carlo Simulations of 100 sample circuits. Transition Statistics for high activity gate 1407 in c2670 for a random vector pair. Histograms obtained from Monte Carlo Simulations of 100 sample circuits. mintran = 0 maxtran =1 0 mintran = 0 maxtran = 8

26 May 14, 2009 26ISVLSI 09 Effect of Inertial Delay… mintran = 0 maxtran = 6 mintran = 0 maxtran = 4

27 Power Estimation Results Circuits implemented using TSMC025 2.5V CMOS library, with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulations were run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM. Circuits implemented using TSMC025 2.5V CMOS library, with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulations were run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM. May 14, 2009 ISVLSI 09 27

28 May 14, 2009 28ISVLSI 09 Zero-Delay Vs. Event-Driven Simulation

29 May 14, 2009 29ISVLSI 09 Conclusion Bounded delay model allows power estimation method with consideration of uncertainties in delays. Bounded delay model allows power estimation method with consideration of uncertainties in delays. Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. Monte Carlo versus min-max analysis: Reduced dimension of sample space - Monte Carlo is over vectors and circuits; min- max is over vectors only. Monte Carlo versus min-max analysis: Reduced dimension of sample space - Monte Carlo is over vectors and circuits; min- max is over vectors only. Future work: (a) Find number of vectors for convergence of result; (b) find probability distribution of power. Future work: (a) Find number of vectors for convergence of result; (b) find probability distribution of power.

30 May 14, 2009 30ISVLSI 09

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