1. © 2001 ® 1 TM NIOS 1.1 Simulation Flow A Step by Step guidelines for both VHDL & Verilog

2. © 2001 ® 2 Directory OrganisationDB1 DB2 DB3

3. © 2001 ® 3 NIOS VHDL Design Flow NIOS Megawizard Update PTF File Result Software Writing Software Writing NIOS-BUILDNIOS-BUILD NIOS-RUNNIOS-RUN Generate_ProjectGenerate_Project VHDL_simulationVHDL_simulation ModelSim Simulation *.do files writing *.do files writing NIOS-BUILDNIOS-BUILD DB1 Quartus Compilation Quartus Programmer Simulation ? DB2 DB3 DB1 DB3 DB2 Software Modification Hardware Modification Requirements Meet Add DO_BUILD_SIM ="1"

4. © 2001 ® 4 Environment prerequisites Nios 1.1 must be installed Copy following files –generate_project –vhdl_simulation –trace2obj in C:\Cygwin\usr\altera\excalibur\nios-sdk\bin

5. © 2001 ® 5 Summary of the tutorial 1.Generating a Nios System Variation 2.Compiling Your Software 3.Modifying the PTF File 4.Generating the Simulation Environment 5.Preparing a Modelsim Script 6.Simulating with Modelsim 7.Tracing Processor’s Activity 8.Generating an EDIF Netlist & Compiling w/ Quartus II 9.Notes

6. © 2001 ® 6 1.Generating a Nios System Variation 1.Open Quartus and Create a New Project  Working Directory: Nios_project  Project Name & Top Level Name: mycpu 2.Launch the MegaWizard Plug-In manager  Create a New Custom Variation of Nios  Give it the name: mycpu  Select ALTERA Excalibur NIOS TM megafunctions  Select Verilog HDL output type 3.Do parameterise your core system, for instance NIOS 32bits, 16bits @, 256 files reg., 3bits shifter, No MSTEP, No MUL Rom_prg, 4K 32bits@= 0x0000, leave blank the contents Ram_sys, 1K 32bits@= 0x1000 Timer@= 0x2000, #IRQ= 20 Led_pio, 4 outputs@= 0x3000 Main Program Memory = rom_prg Main Data Memory= ram_sys Boot Device= rom_prg Int. Vector table loc.= ram_sys Synthesis Target= None "mycpu.ptf" file is generated which describes your whole NIOS system

7. © 2001 ® 7 2.Compiling Your Software Application 1.Create Your C Code (for example, mycode.c) in C:\NIOS_project\mycpu_sdk\src 2.Open a Bash Window & Go in C:\NIOS_project\mycpu_sdk\src 3.Run NIOS-BUILD To Generate Compiled Code –mycode.srec –mycode.objdump

8. © 2001 ® 8 3.Modifying the PTF file 1.Open mycpu.ptf file with vi (or Your Favorite Editor) in C:\Nios_project 2.Turn On Simulation Support File Generation by Setting Variable do_build_sim to 1 As Follows: SYSTEM mycpu { WIZARD_SCRIPT_ARGUMENTS { do_build_sim = "1" ; 3.Rom_prg user file specification  Find the MODULE rom_prg section and Change the following lines WIZARD_SCRIPT_ARGUMENTS { Writeable = "0"; Contents = "user_file"; Initfile = "mycpu_sdk\\src\\mycode.srec"; }

9. © 2001 ® 9 Skip this step if you run a verilog simulation 4.Generating the Simulation Environment 1.Open BASH window and go in c:\NIOS_project\ 2.Run the following command  GENERATE_PROJECT mycpu Only verilog files are generated at this point. 3.VHDL files generation  Go in c:\NIOS_project\mycpu_sim  Run VHDL_SIMULATION mycpu_test_bench.v > compile_vhdl.do

10. © 2001 ® 10 5.Preparing a ModelSim Script 1.VHDL Edit the compile_vhdl.do file  Remove the initial header lines, leaving only the file names  Add vcom -work work for each line  Re-Order memory files included Memory Lanes have to be declared before the memory top level definition  Add vsim work.mycpu_test_bench You should get the following macro file 2.Verilog Create a compile_verilog.do  Add vlog -work work./mycpu_test_bench.v  Add vsim work.mycpu_test_bench cd C:/NIOS_project/mycpu_sim vcom -work work./nios_cpu_dr.vhd vcom -work work./nios_cpu_ar.vhd vcom -work work./nios_cpu_cr.vhd vcom -work work./nios_cpu_register_ram.vhd vcom -work work./nios_cpu_major_opcode_table.vhd vcom -work work./nios_cpu_subtable_w.vhd vcom -work work./nios_cpu_instruction_decoder.vhd vcom -work work./nios_cpu_cpu_core.vhd vcom -work work./timer.vhd vcom -work work./led_pio.vhd vcom -work work./rom_prg.vhd vcom -work work./ram_sys_lane_0.vhd vcom -work work./ram_sys_lane_1.vhd vcom -work work./ram_sys_lane_2.vhd vcom -work work./ram_sys_lane_3.vhd vcom -work work./ram_system.vhd vcom -work work./nios_rg.vhd vcom -work work./nios_pbm.vhd vcom -work work./nios_core.vhd vcom -work work./test_equipment.vhd vcom -work work./mycpu_test_bench.vhd Vsim work.mycpu_test_bench cd C:/NIOS_project/mycpu_sim vcom -work work./nios_cpu_dr.vhd vcom -work work./nios_cpu_ar.vhd vcom -work work./nios_cpu_cr.vhd vcom -work work./nios_cpu_register_ram.vhd vcom -work work./nios_cpu_major_opcode_table.vhd vcom -work work./nios_cpu_subtable_w.vhd vcom -work work./nios_cpu_instruction_decoder.vhd vcom -work work./nios_cpu_cpu_core.vhd vcom -work work./timer.vhd vcom -work work./led_pio.vhd vcom -work work./rom_prg.vhd vcom -work work./ram_sys_lane_0.vhd vcom -work work./ram_sys_lane_1.vhd vcom -work work./ram_sys_lane_2.vhd vcom -work work./ram_sys_lane_3.vhd vcom -work work./ram_system.vhd vcom -work work./nios_rg.vhd vcom -work work./nios_pbm.vhd vcom -work work./nios_core.vhd vcom -work work./test_equipment.vhd vcom -work work./mycpu_test_bench.vhd Vsim work.mycpu_test_bench Compile_vhdl.do

11. © 2001 ® 11 Skip this step if you run a verilog simulation 6.Simulating with ModelSim1/2 1.Launch Modelsim Altera-Edition or SE 5.4 2.Open "File  Change directory…" menu and select C:/NIOS_project/mycpu_sim 3.Open the "Options  Compiler…" menu  Disable "Check for Vital Compliance"  Disable "Optimize for Vital"  Enable "Use 1993 Language Syntax" 4.Type do compile_vhd or do compile_verilog.do in the command line 5.Open the "View  Structure" menu 6.Open the "View  Signal" menu

12. © 2001 ® 12 6.Simulating with ModelSim2/2 1.Select the following signals:  /mycpu_test_bench/the_mycpu_core/clk  /mycpu_test_bench/the_mycpu_core/reset_n  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/irq_number  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/ifetch  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/mem_addr [set the radix format to hex]  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/data_from_cpu [set the radix format to hex]  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/data_to_cpu [set the radix format to hex] 2.In the Waves window, open "Edit  Display Properties…"  Set to 1 the Signal Names path elements displayed 3.In the Waves window, Save your waves format as wave.do 4.Open the "Options  Simulation..." menu and enable "Suppress Warning" for both Synopsys and IEEE packages. 5.Type "run 200µs" in the command line

13. © 2001 ® 13 7.Tracing Processor’s Activity 1/3 The goal is to dump the processor’s activity using assembly code 1.Restart the simulation by typing restart -f 2.Open the "View  list" window 3.In the Waves window, select & slide to the List window the following signals  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/mem_addr (must be first in the list)  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/ifetch 4.Under the List window, open the "Prop  Display Props…" menu and set Signal Names = 1 for path elements displayed. 5.Set the mem_addr signal radix in the list window to Hexadecimal  Select the signal and open "Prop  Signal Props…" and select Hexadecimal  Change width characters displayed to 15. 6.Rerun the simulation as long as you want (200µs)

14. © 2001 ® 14 7.Tracing Processor’s Activity 2/3 7.Under the List window, open the "Prop  Display Props…" menu and select the Triggers Tab. 8.Enable the Trigger Gating and fill the Expression area by:  /mycpu_test_bench/the_mycpu_core/the_mycpu_cpu/ifetch = 1 9.Open "File  Write List (Tabular)" menu and save it as mycode.lst 10.Save your list format as list.do 11.Create a Debug directory in the top working directory c:\NIOS_project\ 12.Move mycode.lst and mycode.objdump The latter is located c:\NIOS_project\mycpu_sdk\src directory 13.Open BASH Window and go under c:\NIOS_project\debug and type  Trace2obj mycode.objdump mycode.lst It will build the mycode.lst-objdump file which represents the processor activity for your simulation.

15. © 2001 ® 15 7.Tracing Processor’s Activity 3/2   NIOS-BUILD mycode.c mycode.objdump mycode.srec mycode.lst TRACE2OBJ 

16. © 2001 ® 16 8.Generating an EDIF & Compiling w/ Quartus II 1.Edit file mycpu.ptf in c:\NIOS_project\ 2.Enable the synthesis by putting skip_synth option to 0 3.Open BASH window and go under c:\NIOS_project\ 4.In the Bash Window, run the following command  GENERATE_PROJECT mycpu 5.In Quartus II, use the generated EDIF in your project

17. © 2001 ® 17 9.Notes Simulating Once the SW Has Been Modified –Step 4 –Type restart –f under Modelsim command line –Type do compile_all.do (or compile_verilog.do) –Type wave.do –Type list.do