1. Boosting: Min-Cut Placement with Improved Signal Delay Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093 abk@cs.ucsd.edu CSE Department University of CA, San Diego La Jolla, CA 92093 sreda@cs.ucsd.edu Igor L. Markov EECS Department University of Michigan Ann Arbor, MI 48109 imarkov@eecs.umich.edu VLSI CAD Laboratory at UCSD

2. Outline  Introduction and motivation  Controlling wirelength distribution  Boosting min-cut placement  Effect of boosting on cut values  Experimental results  Conclusions

3. Introduction: Min-Cut Placement  Min-cut objective: minimize cut partitions → minimizes total wirelength with the help of terminal propagation  Min-cut partitioning produces slicing outlines

4. Introduction: Min-Cut Placement  Min-cut partitioning produces slicing outlines  Min-cut objective: minimize cut partitions → minimizes total wirelength with the help of terminal propagation

5.  Min-cut placers Motivation: Avoiding Global Interconnects severely increase propagation delay since delay is proportional to square of the wirelength take part of critical paths and degrade performance require buffering for electrical sanity have a propagation delay that is equivalent to several clock cycles Conclusion: try to prevent global interconnects  Sequentially minimize wirelength, i.e., the routing demand  Do not treat global interconnects in any special way  Global interconnects can

6. Case A Case B  Cases A and B: same wirelength & number of cuts  Case B: no global interconnects (cf. Case A) Motivation: Example

7. Outline Introduction and motivation  Controlling wirelength distribution  Boosting min-cut placement  Effect of boosting on cut values  Experimental results  Conclusions

8. Bounds on Net Length  A net’s HPWL (Half Perimeter Wirelength) is bounded  from below by distances between closest points of incident partitions  from above by distances between furthest points of incident partitions  These bounds are gradually refined during top-down placement  at the beginning lower bounds are ~0s, upper bounds are determined by placement region  at the end, the bounds are close to (or match) HPWL Upper bound = ¾ chip width Lower bound = ¼ chip width Net L

9. Dichotomy of Lower and Upper bounds Net L Upper bound reduces; lower bound stays the same Net L Upper bound stays the same; lower bound increases

10. Net Extension Control  Partitioning a block extends a net L if the next two equivalent conditions occur: (1) Cutting L increases the lower bound on its length (2) Not cutting L decreases the upper bound on its length Or equivalently  We use the previous conditions to detect net extension and attempt to curb it via boosting

11. Boosting Min-Cut Placement  Boosting = multiplying a hyperedge (net) weight by a factor  boosting factor  Boosting is used only when a cut can increase a lower bound L Boost net L with a boosting factor of 2 L

12. BOOST? YES To Boost or Not to Boost? BOOST? YES NO

13. Effect of Boosting on Cut Value v u  v is connected to a net eligible for boosting, u is not  either can be moved to the right  Boosting factor is 2: the gain of v grows from 1 to 2  Tie is broken by moving v → no degradation in wirelength, and a global wire is avoided Case 1

14. Effect of Boosting on Cut Value v u  v is connected to several nets eligible for boosting, u is not  Boosting factor is 2 on each net: v’s gain grows from 3 to 6  v has a higher priority → no degradation in wirelength and a global interconnect is eliminated Case 2

15. Effect of Boosting on Cut Value v u  v is connected to 2 nets eligible for boosting  Boosting factor is 2  gain for v increases (from 2 to 4); gain for u is the same (3)  v is moved → wirelength is degraded but global wires are prevented Case 3

16. Summary  Boosting helps in eliminating global interconnects  Boosting may degrade wirelength in some cases  To reduce wirelength degradation, we only boost during first 8 levels  That is where long wires are determined anyway  At the 8 th placement level: → The average block perimeter is 1/256 of the original chip perimeter → Global interconnects are already established → No point in further boosting

17. Outline Introduction and motivation Controlling wirelength distribution Boosting min-cut placement Effect of boosting on cut values  Experimental results  Conclusions

18. Experimental Setup BenchmarkCellsNetsCore regionWhitespaceMetal layers Clock period A 21103212302142x196913.5%49.456 B 339173915323157x1273249.8%430.962 C 9585103988705x8696829.7%537.515  Three industrial benchmarks  Two experiments:  Effect of boosting on the wirelength distribution  Effect of boosting on timing

19. Experimental Results: Wirelength Histogram (Design A) Percentage change in number of nets (%) Bins (in terms of half the chip’s perimeter) Boosting substantially reduces global interconnects

20. Experimental Results: Wirelength Histogram (Design B) Percentage change in number of nets (%) Bins (in terms of half the chip’s perimeter) Boosting substantially reduces global interconnects

21. Experimental Results: Timing benchmarkFlowWirelengthSlack (ns)TNS (ns) ToolMode AIndustNTD3491503-0.66028.107 TD3570024-0.36812.022 CapoRegular3335483-0.60723.360 Boost3260184-0.3425.107 BIndustNTD9080259-31.79368253.5 TD9100552-31.75056618.6 CapoRegular8375939-29.59544951.8 Boost8711281-25.75749627.6 CIndustNTD839408-1.8821870.3 TD841585-1.8781750.8 CapoRegular835962-1.8751810.6 boost872089-1.8781799.5

22. Conclusions and Future work  By tracking lower/upper bounds, we identify potential long wires  By additionally increasing net weights, we decrease # of long wires  This alters wirelength distribution and reduces global interconnects  Routability is slightly affected, but generally preserved  Boosting tends to improve circuit delay (timing) measured by the worst slack and total negative slack (TNS)  Ongoing work examines the impact of boosting on the number of inserted buffers

23. Thank you for your attention