1. Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES

2. Digital Integrated Circuits© Prentice Hall 1995 Memory Chapter Overview

3. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Classification

4. Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Architecture: Decoders

5. Digital Integrated Circuits© Prentice Hall 1995 Memory Array-Structured Memory Architecture

6. Digital Integrated Circuits© Prentice Hall 1995 Memory Hierarchical Memory Architecture

7. Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Timing: Definitions

8. Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Timing: Approaches

9. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM

10. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout

11. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout

12. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM

13. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM Layout

14. Digital Integrated Circuits© Prentice Hall 1995 Memory Equivalent Transient Model for MOS NOR ROM

15. Digital Integrated Circuits© Prentice Hall 1995 Memory Equivalent Transient Model for MOS NAND ROM

16. Digital Integrated Circuits© Prentice Hall 1995 Memory Propagation Delay of NOR ROM

17. Digital Integrated Circuits© Prentice Hall 1995 Memory Decreasing Word Line Delay

18. Digital Integrated Circuits© Prentice Hall 1995 Memory Precharged MOS NOR ROM

19. Digital Integrated Circuits© Prentice Hall 1995 Memory Floating-gate transistor (FAMOS)

20. Digital Integrated Circuits© Prentice Hall 1995 Memory Floating-Gate Transistor Programming

21. Digital Integrated Circuits© Prentice Hall 1995 Memory FLOTOX EEPROM

22. Digital Integrated Circuits© Prentice Hall 1995 Memory Flash EEPROM

23. Digital Integrated Circuits© Prentice Hall 1995 Memory Cross-sections of NVM cells EPROMFlash Courtesy Intel

24. Digital Integrated Circuits© Prentice Hall 1995 Memory Characteristics of State-of-the-art NVM

25. Digital Integrated Circuits© Prentice Hall 1995 Memory Read-Write Memories (RAM)

26. Digital Integrated Circuits© Prentice Hall 1995 Memory 6-transistor CMOS SRAM Cell

27. Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Write)

28. Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Read)

29. Digital Integrated Circuits© Prentice Hall 1995 Memory 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

30. Digital Integrated Circuits© Prentice Hall 1995 Memory Resistance-load SRAM Cell

31. Digital Integrated Circuits© Prentice Hall 1995 Memory 3-Transistor DRAM Cell

32. Digital Integrated Circuits© Prentice Hall 1995 Memory 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

33. Digital Integrated Circuits© Prentice Hall 1995 Memory 1-Transistor DRAM Cell

34. Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Cell Observations

35. Digital Integrated Circuits© Prentice Hall 1995 Memory 1-T DRAM Cell

36. Digital Integrated Circuits© Prentice Hall 1995 Memory SEM of poly-diffusion capacitor 1T-DRAM

37. Digital Integrated Circuits© Prentice Hall 1995 Memory Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode

38. Digital Integrated Circuits© Prentice Hall 1995 Memory Periphery

39. Digital Integrated Circuits© Prentice Hall 1995 Memory Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

40. Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic Decoders

41. Digital Integrated Circuits© Prentice Hall 1995 Memory A NAND decoder using 2-input pre- decoders

42. Digital Integrated Circuits© Prentice Hall 1995 Memory 4 input pass-transistor based column decoder

43. Digital Integrated Circuits© Prentice Hall 1995 Memory 4-to-1 tree based column decoder

44. Digital Integrated Circuits© Prentice Hall 1995 Memory Decoder for circular shift-register

45. Digital Integrated Circuits© Prentice Hall 1995 Memory Sense Amplifiers

46. Digital Integrated Circuits© Prentice Hall 1995 Memory Differential Sensing - SRAM

47. Digital Integrated Circuits© Prentice Hall 1995 Memory Latch-Based Sense Amplifier

48. Digital Integrated Circuits© Prentice Hall 1995 Memory Single-to-Differential Conversion

49. Digital Integrated Circuits© Prentice Hall 1995 Memory Open bitline architecture

50. Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Read Process with Dummy Cell

51. Digital Integrated Circuits© Prentice Hall 1995 Memory Single-Ended Cascode Amplifier

52. Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Timing

53. Digital Integrated Circuits© Prentice Hall 1995 Memory Address Transition Detection

54. Digital Integrated Circuits© Prentice Hall 1995 Memory Reliability and Yield

55. Digital Integrated Circuits© Prentice Hall 1995 Memory Open Bit-line Architecture —Cross Coupling

56. Digital Integrated Circuits© Prentice Hall 1995 Memory Folded-Bitline Architecture

57. Digital Integrated Circuits© Prentice Hall 1995 Memory Transposed-Bitline Architecture

58. Digital Integrated Circuits© Prentice Hall 1995 Memory Alpha-particles

59. Digital Integrated Circuits© Prentice Hall 1995 Memory Yield Yield curves at different stages of process maturity (from [Veendrick92])

60. Digital Integrated Circuits© Prentice Hall 1995 Memory Redundancy

61. Digital Integrated Circuits© Prentice Hall 1995 Memory Redundancy and Error Correction

62. Digital Integrated Circuits© Prentice Hall 1995 Memory Programmable Logic Array

63. Digital Integrated Circuits© Prentice Hall 1995 Memory Pseudo-Static PLA

64. Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic PLA

65. Digital Integrated Circuits© Prentice Hall 1995 Memory Clock Signal Generation for self-timed dynamic PLA

66. Digital Integrated Circuits© Prentice Hall 1995 Memory PLA Layout

67. Digital Integrated Circuits© Prentice Hall 1995 Memory PLA versus ROM

68. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years

69. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation

70. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Technology feature size for different SRAM generations