1. EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 22 Nov. 17, 2005 1.Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational Blocks 6.Latches and Flip Flops 7.Registers and Counters Reading: Hambley 12.7, 7

2. EE42/100 Fall 2005 Prof. Fearing 2 Decoder n inputs, 2 n outputs –one output is 1 for each possible input pattern, all other outputs are 0 ABAB 12341234

3. EE42/100 Fall 2005 Prof. Fearing 3 Multiplexer (MUX) n-bit selector and 2 n inputs, one output –output equals one of the inputs, depending on selector I1I2I3I4I1I2I3I4 2 input decoder ABAB O

4. EE42/100 Fall 2005 Prof. Fearing 4 Flip-Flops One of the basic building blocks for sequential circuits is the flip-flop: –2 stable operating states  stores 1 bit of info. –A simple flip-flop can be constructed using two inverters: Q Q

5. EE42/100 Fall 2005 Prof. Fearing 5 Realization of the S-R Flip-Flop S R Q Q RSQnQn 00Q n-1 011 100 11(not allowed) S R Q Q S-R Flip-Flop Symbol:

6. EE42/100 Fall 2005 Prof. Fearing 6 Clocked S-R Flip-Flop When CK = 0, the value of Q does not change When CK = 1, the circuit acts like an ordinary S-R flip-flop S R Q Q CK time vC(t)vC(t) V OH 0 TCTC 2T C positive-going edge (leading edge) negative-going edge (trailing edge)

7. EE42/100 Fall 2005 Prof. Fearing 7 The output terminals Q and Q behave just as in the S-R flip-flop. Q changes only when the clock signal CK makes a positive transition. The D (“Delay”) Flip-Flop D CK Q D Flip-Flop Symbol: Q CKDQnQn 0  Q n-1 1   00  11

8. EE42/100 Fall 2005 Prof. Fearing 8 D Flip-Flop Example (Timing Diagram) t CK t D t Q

9. EE42/100 Fall 2005 Prof. Fearing 9 RSRSRS DQDQDQDQ OUT1OUT2OUT3OUT4 CLK IN1IN2IN3IN4 RS "0" Registers A register is an array of flip-flops that is used to store or manipulate the bits of a digital word. Example: 4 bit data register

10. EE42/100 Fall 2005 Prof. Fearing 10 Registers Example: Serial-In, Parallel-Out Shift Register D0D0 CK Q0Q0 Data input Clock input D1D1 CK Q1Q1 D2D2 Q2Q2 Q0Q0 Q1Q1 Q2Q2 Parallel outputs RSRSRS DQDQDQDQ Clock IN1 RS Reset “0” “0” literal IN2 IN3IN4 Load/Shift Output mux Parallel to serial converter

11. EE42/100 Fall 2005 Prof. Fearing 11 parallel inputs parallel outputs serial transmission Shift Register Application Parallel-to-serial conversion for serial transmission

12. EE42/100 Fall 2005 Prof. Fearing 12 Finite State Machine Block diagram/Counter example Inputs (N) outputs Clock Current state of the system: Q n (M states) Clock Combinatorial Logic Register (N+M edge triggered flip-flops) Q n+1 Counter Clock Q2 Q1 Q0 Q2Q2 Q1Q1 Q0Q0 Q2Q2 Q1Q1 Q0Q0 present state next state NS=PS+1 (good for freq division, position, velocity sensing)