1. Generating Code From DAGs Directed Ascyclic Graph (DAG) A tree structure such that nodes may have more than one parent Multiple parents are allowed so that an expression can be used more than once

2. Redundant Expressions DAG for (a+b)+(a+b) b + a +

3. Updated Variables The expression i = i + 1 with updated variable highlighted 1 +(i) i

4. Code to Optimize g = c * (a + b) + (a + b) c = a + b a = (c * d) + (e – f)

5. Convert Code to Trees + = g + * + c b a ba + = c d c + = a – * f e b a

6. Convert Tree to DAG + (G) * + c b a * + (C)+ (C) c b a * + (C)+ (C) c – * f e d +(A) b a

7. Schedule DAG Nodes The first operator scheduled will be the last evaluated Because a DAG can have more than one root, start at rightmost root Nodes are added to DAG from left to right, so rightmost is the last to be created and added to graph Work left-to-right within sub-DAG scheduling each operator in turn Within a sub-DAG, schedule an operator if all of its parents have been scheduled

8. Scheduled Nodes b a + 4 (G) * 5 + 6 (C) c – 3 * 2 f e d + 1 (A)

9. Determining Virtual Registers Start at node with schedule number 1 Assign the node that currently has the lowest schedule number m and has not already been assigned to a register set to the next sequential virtual register set Vn, where n = 1,2, … Recursively assign each left node in the tree under m to virtual register set Vn so long as its lowest schedule number parent belongs to Vn Continue until all nodes are assigned virtual regisers

10. Virtual Registers Assigned b a + 4 (G) V3 * 5 V3 + 6 (C) V1 c – 3 V2 * 2 V1 f e d + 1 (A) V1

11. Virtual Register Span A virtual register’s span is the nodes it is needed for Two virtual registers may be mapped into the same hardware registers if their spans do not overlap V1 is mapped alone to R1 since its span is from node 1 to node 6 V2 and V3 are mapped into R2 since their spans do not overlap RegisterSpan V1 V2 V3 1-6 1-3 4-5

12. Code Generation Generate code from highest schedule number to lowest schedule number Make sure that register that is saved is real register that virtual register at that node maps to Delay stores until code for lowest schedule number parent is about to be output

13. Code Generation (1) Load a, r1(7) Load e, r2 (2) Add b, r1(8) Sub f, r2 (3) load c, r2(9) Store c, r1 (4) Mult r1, r2(10) Mult d, r1 (5) Add r1, r2(11) Add r2, r1 (6) Store g, r2(12) Store a, r1 b a + 4 (G) r2 * 5 r2 + 6 (C) r1 c – 3 r2 * 2 r1 f e d + 1 (A) r1

14. Node Scheduling c b d + 4 + 3 * 2 a + 1 c b + 4 + 3 * 2 + 1 da a * (b + c) + (b + c) + d(b + c) * a + d + (b + c)

15. Virtual Registers c b d + 4 V3 + 3 V2 * 2 V1 a + 1 V1 c b + 4 V1 + 3 V2 V1 * 2 + 1 V1 da RegisterSpan V1 V2 V3 1-2 2-4 3-4 RegisterSpan V1 V2 1-4 1-3

16. Real Registers c b d + 4 R3 + 3 R2 * 2 R1 a + 1 R1 c b + 4 R1 + 3 R2 R1 * 2 + 1 R1 da

17. Code Comparison Load b, r3Load b, r1 Add c, r3Add c, r1 Move r3, r2Load d, r2 Add d, r2Add r1, r2 Load a, r1Mult a, r1 Mult r3, r1Add r2, r1 Add r2, r1

18. Aliasing When aliasing is included in DAGs, code generation becomes more complicted For example, assignment to one array element, say a(i) may effect the value of a seemingly different array element, a(j) DAGs must be generated so that aliasing is handled

19. Problems 1.Stores cannot be delayed. For example, a(i) = j must be stored immediately, because later a(k) could be referenced where i = k 2.An assignment to an alias must kill all previous references to that alias. For example a(i) = j; a(k) = m; /* this kills the association of j with a(i) */ 3.The order of writes to, and reads from, aliased data objects must be preserved

20. DAG for j = a(i) i a Ind  (j)

21. DAG for a(i) = j i a Ind (%1)

22. DAG for a(i) = j i a Ind (%1) j (%1  ) DAG for a(k) = m k a Ind (%1) m (%2  )

23. DAG for a(i) = j; k = a(m); i a Ind (%1) j(%1  ) m a Ind (%2)  (k) i a Ind (%1) m a Ind (%2)  (k) j(%1  )