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234262 Tutorial #13 Solving MIPS Exam Problems 20:00 234262 © Dima Elenbogen 2010, Technion 1.

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Presentation on theme: "234262 Tutorial #13 Solving MIPS Exam Problems 20:00 234262 © Dima Elenbogen 2010, Technion 1."— Presentation transcript:

1 234262 Tutorial #13 Solving MIPS Exam Problems 20:00 234262 © Dima Elenbogen 2010, Technion 1

2 LWA Ri, Rj 20:00234262 © Dima Elenbogen 2010, Technion2

3 קידוד של LWA Ri, Rj 20:00234262 © Dima Elenbogen 2010, Technion 3

4 קידוד של LWA Ri, Rj 20:00234262 © Dima Elenbogen 2010, Technion4

5 מהלך הביצוע של LWA Ri, Rj 20:00234262 © Dima Elenbogen 2010, Technion5

6 מימוש LWA Ri, Rj 234262 – © Dima Elenbogen 2010 Technion - IIT

7 למה נחוץ מחזור ההמתנה ? 20:00234262 © Dima Elenbogen 2010, Technion7 Tpd Tpd ≈ Tcycle

8 LWC Rn, const 20:00234262 © Dima Elenbogen 2010, Technion8 Pay attention that this command occupies 2 words!

9 קידוד של LWC Rn, const 20:00234262 © Dima Elenbogen 2010, Technion9 OPRsRtIM OP...Rn1 6 bit5 bit 16 bit const 32 bits α:α: α+4:

10 רעיון למימוש של LWC Rn, const 20:00234262 © Dima Elenbogen 2010, Technion10 IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU OPRsRtIM OP...Rn1 Const למה קידדנו את Rn דווקה ב -Rt?

11 שלב decode מקורי 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR 5 IR[t] 5 IR[s] N REG1 RsRs RtRt M5 M5 M6 M6 ALUALU N REG2 REG FILE 16 IR[IM] 44 SIGN EXT C1 6 IR[OP] ALUout BPCBPC PCPC C1 is decoding IR[OP] Rs is being read Rt is being read BPC ← PC + SX(Imm)*4

12 תוספת בשלב decode 234262 – © Yohai Devir 2007 Dima Elenbogen 2010 Technion - IIT IRIR M5 M5 M6 M6 ALUALU 16 IR[IM] 44 SIGN EXT C1 6 IR[OP] ALUout BPCBPC PCPC IRIR M5 M5 M6 M6 ALUALU PCPC M1 M1 M2 M2 ADDR MEMout MEM WDATA C1 is decoding IR[OP]... BPC ← PC + SX(Imm)*4 MEMout <= MEM(PC) // BPC ← α + 8 // Read the const value from the memory השינוי לא פוגע בפקודות אחרות ! OPRsRtIM OP...Rn1

13 שלב ייחודי ל - LWC Rn, const M2 M2 5 IR[d] REG FILE ADDR MEMout MEM WDATA PCPC M1 M1 20:00234262 © Dima Elenbogen 2010, Technion13 Rt ← Mem(PC) PC ← BPC WB: // Rt ← MEM[α + 4] // PC ← α + 8 IRIR M3 M3 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ALUALU OPRsRtIM OP...Rn1

14 מימוש של LWC Rn, const 20:00234262 © Dima Elenbogen 2010, Technion14 OPRsRtIM OP...Rn1 6 bit5 bit 16 bit const 32 bits IR ← Mem(PC) PC ← PC + 4 Fetch: // PC ← α + 4 C1 is decoding IR[OP]... BPC ← PC + SX(Imm)*4 MEMout <= MEM(PC) // BPC ← α + 8 // Read the const value Decode: Rt ← Mem(PC) PC ← BPC WB: // Rt ← MEM[α + 4] // PC ← α + 8 פעולה נוספת ב - decode

15 שלב ייחודי אלטרנטיבי ל - LWC Rn, const 20:00234262 © Dima Elenbogen 2010, Technion15 Rt ← Mem(PC) PC ← PC + 4 WB: // Rt ← MEM[α + 4] // PC ← α + 8 OPRsRtIM OP...Rn... IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU

16 ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion16

17 קידוד ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion17 OPRsRtIM OPRiRjImm 6 bit5 bit 16 bit IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU

18 IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU פיתרון קל ל - ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion18

19 IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 N REG1 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU עלות הפיתרון הקל ל - ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion19 קל, אך יקר. עלותו היא 2*32+32 = 96 ש '' ח. דורש 4 מחזורים.

20 N REG1 0 IRIR M3 M3 5 IR[d] 5 IR[t] 5 IR[s] M4 M4 W DATA M5 M5 R s R t M6 M6 12 IR[OP+FUN] N REG2 16 IR[IM] WN REG ZERO REG FILE 4 44 SIGN EXT C1 C3 WRITEWRITE 6 IR[OP] ALUout BPCBPC PCPC M1 M1 M2 M2 ZERO IR[XI] 26 PC[31:28] C2 2 0 4 WRITEWRITE READREAD ALUout ADDR MEMout MEM WDATA ALUALU פיתרון בינוני ל - ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion20 עלות בינונית : היא 2*32+5 = 69 ש '' ח. אין לנו קבוע 0 בקידוד הפקודה, לכן נדרש בורר לפני REG1. הפיתרון דורש יותר מ -4 מחזורים. כתובת שאליה נכתוב נשמרת ב -PC. כמובן, חובה לשחזר את ערך ה -PC הקודם לאחר השלמת עידכון הזיכרון. BPC ישמש לכך.

21 הפיתרון הזול ביותר ל - ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion21 OPRsRtIM OPRiRjImm

22 הפיתרון הזול ביותר ל - ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion22

23 הפיתרון הזול ביותר ל - ADDMEM Ri, Rj, Imm 20:00234262 © Dima Elenbogen 2010, Technion23 מחזורי קריאת רגיסטרים חדשים מחזור קריאת רגיסטרים אחרי עידכון מחזורי קריאת רגיסטרים חדשים שימו לב לכתיבות שנעשות במקביל במחזור הלפני אחרון מחזורים 3, 13 ו -14: גיבוי ערך PC ב -BPC ושיחזור הערך משם

24 Pipelined MIPS 20:00234262 © Dima Elenbogen 2010, Technion24 IFIDEXMEMWB The main problem of the pipelined MIPS are data hazards. If a command updates Rk, its new value will become available only 3 commands later. A compiler/programmer should optimize code in order to minimize the data hazards. When they are inevitable, 2 solutions are possible: The compiler/programmer can intentionally insert NOP commands. (In reality) If a processor has a data hazard detection unit, the unit should detect the hazards and delay processing of the reading commands.

25 SWI Rj Rk 20:00234262 © Dima Elenbogen 2010, Technion25

26 קידוד של SWI Rj Rk 20:00234262 © Dima Elenbogen 2010, Technion26 OPRsRtIM OPRjRk4 6 bit5 bit 16 bit

27 SWI Rj Rk 20:00234262 © Dima Elenbogen 2010, Technion27 OPRsRtIM OPRjRk4 6 bit5 bit 16 bit

28 מימוש של SWI Rj Rk 20:00234262 © Dima Elenbogen 2010, Technion28

29 תשובה ל - SWI Rj Rk 20:00234262 © Dima Elenbogen 2010, Technion29

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