2. טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Characterization presentation Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004

3. Memory Controller for Satellite Problems In Space Short time “ Bit Flips ” Permanent malfunction – “ Latch Ups ” Memory is especially vulnerable to these kind of failures !

4. Memory Controller for Satellite Block Diagram of Conventional Memory System PowerPC405 ( CPU ) SDRAM Memory PLB Memory Controller

5. Memory Controller for Satellite Block Diagram of a Memory System using TMR with 3 Conventional Controllers PowerPC405 ( CPU ) SDRAM Memory PLB Memory Controller 1 SDRAM Memory Controller 2 Memory Controller 3 TMR Unit SDRAM Memory

6. Memory Controller for Satellite Block Diagram of a Memory System using TMR – Transparent Approach PowerPC405 ( CPU ) SDRAM Memory SDRAM Memory SDRAM Memory Controller PLB EDAC

7. Memory Controller for Satellite Block Diagram of a Memory System using TMR – Transparent Approach separating data and code PowerPC405 ( CPU ) SDRAM Memory (data) PLB - DATA SDRAM Memory (data) SDRAM Memory (data) Memory Controller SDRAM Memory (code) PLB - Inst EDAC

8. Memory Controller for Satellite First Semester Goals Study the Virtex-II Pro component design. Study the PPC405 Processor core Study the VHDL development environment and VHDL. Implementation of a basic application over a complete computer system ( without redundancy ). Implementing a first draft of a simple reliable memory system. Midterm Final

9. Memory Controller for Satellite Second Semester Goals Study the probability model of error in a memory system in space. Review different options of possible memory controllers and EDAC in means of optimal BER. Implementation of the optimal (if possible) memory controller and EDAC unit. Debug. System integration of the memory system in a complete computer system.