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Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

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1 Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2

2 Implementing Logic Gates and Circuits Logic With Relays Integrated Circuit Implementation of Gates Transistor-Transistor Logic (TTL) Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

3 Relays Normally Open Relay A B C A B C Normally Closed Relay A-B closed when C = 1 (current through coil) A-B open when C = 1 (current through coil)

4 NOT Gate 5V X Y 0 1 closed open X Y 0101 1010

5 NOT Gate 5V X Y 0 1 closed open X Y 0101 1010

6 AND Gate X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 5V X Y Z

7 AND Gate X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 5V X Y Z 0 0

8 AND Gate X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 0 1

9 AND Gate X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 1 0

10 AND Gate X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 X Y Z 1 1

11 OR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 5V X Y Z X Y Z

12 OR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 5V X Y Z X Y Z 0 0

13 OR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Y Z 0 1

14 OR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Y Z 1 0

15 OR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Y Z 1 1

16 Implementing Gates Using MOSFET Integrated Circuits Relays Normally open Normally closed A B C A B C A B C nMOS transistor A-B closed when C = 1 (normally open) pMOS transistor A-B closed when C = 0 (normally closed)

17 NOT Gate 5V XY Y = ~X X Y X Y 0101 1010

18 NOT Gate 5V XY Y = ~X X Y 0 1 X Y 0101 1010

19 NOT Gate 5V XY Y = ~X X Y 1 0 X Y 0101 1010

20 NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0

21 NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 0 0

22 NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 0 1

23 NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 1 0

24 NAND Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 1 1

25 NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0

26 NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 0 0

27 NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 0 1

28 NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 1 0

29 NOR Gate X Y Z 5V X Y Z X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 1 1

30 AND Gate X Y 5V Z NAND-NOT

31 OR Gate X Y 5V Z NOR-NOT

32 Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates to arithmetic logic units Becoming obsolete with the development of programmable logic devices (PLDs)

33 TTL Chips

34 TTL NAND, NOR, XOR

35 TTL Multiple-input Gates

36 Small-Scale Integrated (SSI) Circuits 1 to 10 gates NAND gate has 4 transistors

37 Medium-Scale Integrated (MSI) Circuits 10-100 gates Adders Comparators Multiplexers Decoders

38 Large-Scale Integrated (LSI) Circuits 100-1000 gates Arithmetic Logic Units

39 Very-Large-Scale Integrated (VLSI) Circuits >1000 gates Microprocessors Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

40 Basic PLD Structure

41 Alternate PLD Representation

42 PLD Connections for XOR

43 1975 – Signetics invents the FPLA

44 1978 – MMI introduces the PAL

45 1983 – AMD introduces the 22V10 1984 – Lattice introduces the GAL – an electrically erasable PAL

46 The GAL 16V8 1 2 3 4 5 6 7 9 1011 12 8 19 20 17 18 15 16 13 14 GND Vcc I/CLK II/O I I I I I I I I/OE I/O GAL 16V8

47 Structure of the GAL 16V8 PLD

48 GAL 16V8 Input Buffer

49 Structure of the GAL 16V8 PLD

50 GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A ­ open B = 1 C = ~A Polarity Pin

51 Structure of the GAL 16V8 PLD

52 XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE 1149.1 JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

53 XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

54 XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288

55 Xilinx 95108 6 function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

56 Architecture of the Xilinx XC95108 CPLD

57 PLDT-3 Xilinx XC95108 CPLD 7 segment display Switches LEDs Buttons

58 PLDT-3 12 macro cells connected to I/O pins 4 pushbuttons 8 toggle switches 8 dip switches 16 LEDs 2 7-segment displays On-board clock signals (4 MHz and 1 Hz)

59 FPGAs Field Programmable Gate Arrays

60 1985 – Xilinx introduces the LCA (Logic Cell Array) The Xilinx XC3000 CLB (configurable logic block).

61 Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) 1991 – Xilinx introduces the XC4000 Architecture XC4003 contained 440,000 transistors 0.7-micron process

62 XC4000E/X Configurable Logic Blocks 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset

63 Look Up Tables  Capacity is limited by number of inputs, not complexity  Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1... 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !

64 What’s Really In that Chip? CLB (Red) Switch Matrix Long Lines (Purple) Direct Interconnect (Green) Routed Wires (Blue) Programmable Interconnect Points, PIPs (White)

65 1998 – Xilinx introduces the Virtex®™ FPGA family 0.25-micron process

66 2003 – Xilinx introduces the Spartan®™-3 family of products Very low cost World’s first 90 nm FPGA

67 Block diagram of Xilinx Spartan IIE FPGA

68 Each Spartan IIE CLB contains two of these CLB slices

69 Block diagram of Xilinx Spartan-3 FPGA

70 Each Spartan-3 CLB contains four CLB slices

71 CPLDs vs. FPGAs

72 x Xilinx will release the world’s first one-billion transistor device this year

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