1. 1 1 Avinoam Kolodny Technion – Israel Institute of Technology Intel PVPD Symposium July 2006 Issues in the Design of Wires

2. 2 2 Thanks to my students and collaborators Anastasia Barger Shay Michaely Konstantin Moiseev Nir Magen Michael Moreinis Arkadiy morgenshtein David Goren Shmuel Wimer Uri Weiser Nachum Shamir Israel Wagner Ran Ginosar Eby Friedman

3. 3 3 Connectivity and Complexity

4. 4 4 What are the issues with wires?  Delay  Power  Noise  Reliability  Cost

5. 5 5 Scope of this talk  Interconnect delay  Interconnect Power

6. 6 6 Sizing and spacing of uniform bus wires

7. 7 7 RC wire delay model N wires W S A Wires do not scale well!

8. 8 8 Coupling capacitance typically dominates W S A

9. 9 9 Data Rate Optimization in an Interconnect Channel  Increase N by:  making the wires narrow (small W),  and dense (small S)  What will happen to the delay? N wires W S A * A. Barger, D. Goren, A. Kolodny, “Simple Design Criterion for Maximizing Data Rate in NoC links”, SPI 2006.

10. 10 Data Rate vs. Wire Width (W) and Spacing (S) T=1  m, H=1  m, A=60  m, l=2mm. S [  m]W [  m] Rough Approximation:

11. 11 What about the speed of light?  Assume S=W RLC RC W=S [u] RC model is unrealistic here!

12. 12 Evolution of Wire Delay Models *Source: E. G. Friedman, U. or Rochester

13. 13 RLC delay model Approximation  Inductive effects:  Longer delay  Steeper slope  overshoot RC delay RLC delay * Eby G. Friedman, Yehea E. Ismail, On- chip inductance in high speed integrated circuits, 2001 L,C and R are per unit length l denotes wire length RC model RLC model

14. 14 Choosing Wire Width and Spacing for maximal Data Rate T=1  m H=1  m, A=60  m,l=2mm. RC model RLC model

15. 15 A simple criterion to choose wire width for peak data rate  Assume S=W time_of_flight RC_delay=0.37RCl 2 RC regionRLC region * A. Barger, D. Goren, A. Kolodny, “Simple Design Criterion for Maximizing Data Rate in NoC links”, SPI 2006.

16. 16 Peak data rate is near RC/RLC boundary RLC RC RC model is O.K. RC model is unrealistic here Simple Criterion for Maximal Data Rate RC regionRLC region W*

17. 17 We know how to extract C, but what about L? l is the wire length c 0 is the speed of light in vacuum  r is the dielectric coefficient of the insulator L and C are per unit length propagation speed in the wire is L total and C total are for the whole wire

18. 18 Fast wires must use transmission line layout  Ground plane and/or wires provide current return path w tg GROUND wg t h SS ws t wg tg GROUND h SS d h wg w SIGNAL GROUND t tg h wg w SIGNAL GROUND t tg ws t d

19. 19 Slower propagation because of Crossing Lines  Crossing lines increase the capacitance, but….  They do not provide a return path for the signal current  They do not reduce inductance  Time of flight (T OF ) becomes longer !  Extract capacitance C RETURN (by ignoring the crossing lines in the layout) to estimate the longer T OF from this expression: Crossing Lines Ground Plane * A. Barger, D. Goren, A. Kolodny, “Simple Design Criterion for Maximizing Data Rate in NoC links”, SPI 2006.

20. 20 conclusions on uniform buses  Most wires operate at the RC region  Simple criterion for peak data rate ensures this  Most wires are laid out at higher density, and operate more slowly  RLC model is necessary only for a few wires  When propagation speed is important  Make them wide and thick to reduce R  Use Transmission line layout for these wires!

21. 21 Sizing and spacing of individual wires in interconnect channels

22. 22 Should all wires be the same? How about optimizing individual widths and spaces? N wires W S l A Strong driver Weak driver A is a fixed constraint

23. 23 Interconnect channel structure * S. Wimer, S. Michaely, K. Moiseev and A. Kolodny, "Optimal Bus Sizing in Migration of Processor Design", IEEE Transactions on Circuits and Systems – I, vol. 53. no. 5, May 2006.

24. 24 Delay Model for wire i

25. 25 Timing Objectives for interconnect channel Optimization all Objective Functions are convex total sum of delays total sum of slacks max delay worst negative slack

26. 26 Minimizing Total Sum of Delays (or Slacks) ( equivalent to minimizing the average wire delay)  Objective: minimize  Total channel width constraint:  At optimum :  This leads to algebraic equations in 2n+2 variables: Unique global optimum!

27. 27 Minimizing the Maximal Delay (MinMax problem) (Optimizing the worst-case wire)  This objective function is not differentiable: no analytic solution  Theorem: In the optimal MinMax solution, the delays of all the wires are equal Objective: minimize Same constraint:

28. 28 Why all wires become equally critical in MinMax solution?  Iteratively allocate more and more area resources to the slowest wire  The critical wire will improve  Its neighbors will lose these resources …  Until the neighbors become critical too L A L A Critical wire L A

29. 29 Iterative Algorithm (Wire sizing and spacing for MinMax Delay) 1.Set initial solution 2.Equalize all delays (iteratively) 3.Apply ‘area preserving local modification’ 4.Go to 2 if 3 yielded max delay reduction

30. 30 Example: Minimizing the worst slack  Cross section of bus wires after MinMax slack optimization, assuming a critical signal (required early) in the middle. Distance from sidewall [  m ] Required delay [ps] Obtained delay [ps]

31. 31 Interleaved bus example (odd-numbered drivers are strong, even-numbered drivers are weak) Distance from sidewall [  m ] Widths [  m ] Spaces [  m ] Delays [ ps ] Widths [  m ] Spaces [  m ] Delays [ ps ] After total sum of delays minimization: After MinMax (worst case wire delay) minimization:

32. 32 Relation Between Minimal Total Sum and MinMax  Which kind of optimization is more useful in practice?

33. 33 Effect of the constraint A

34. 34 Migration of a bus in 65nm technology [

35. 35 Conclusions on optimizing individual wire widths and spaces  Some performance improvement by wire sizing/spacing, according to individual signal slack, driver resistance, etc.  Sum-of-delays is a useful objective for minimization  Very appropriate for automated migration of layout to a new process

36. 36 What else can we do with wires in an interconnect channel?

37. 37 12341234 13241324 Wire reordering (permutation)

38. 38 Reordering of wires to improve the optimal delay

39. 39 Which order is better? Best order!Worst order

40. 40 The idea behind net reordering  Arrange nets by driver resistance such that cross-capacitances are shared optimally

41. 41 Symmetric Hill Order  Take wires sorted in descending order of driver resistance and put alternately to the left and right sides of the bus channel  Obtained permutation of wires is called Symmetric Hill order 7 6 5 4 3 2 1 Symmetric Hill order provides best sharing of inter-wire spaces R drive r

42. 42 Optimal order theorem  given an interconnect channel whose wires are of uniform width W, ‘Symmetric Hill’ order of signals yields minimum total sum of delays (after spacing optimization). R driver * K. Moiseev, S. Wimer and A. Kolodny, “Timing Optimization of Interconnect by Simultaneous Net-Ordering, Wire Sizing and Spacing,” ISCAS 2006.

43. 43 Optimal order in more general cases?  Symmetric Hill was proven optimal for most practical cases (total sum of delay minimization)  Example: 20 sets of 5 wires  R dr : [0.1 ÷ 2] KΩ (random)  C l : [10 ÷ 200] fF (random)  Bus length: 600 μm  Bus width: 12 μm  Technology: 90 nm  A good heuristic:  Don’t try all permutations!  1) Put the signals in symmetric hill of their drivers  2) Perform optimization of widths and spaces

44. 44 Symmetric Hill for MinMax delay?  Not necessarily optimal  BUT:  Was found optimal for most practical cases  It is a good heuristic  In fact, the MinMax delay is very sensitive to wire reordering  Symmetric hill is also good for reducing delay uncertainty because of crosstalk noise

45. 45 Delay improvement by reordering (65nm technology, examples of 5 wires)

46. 46 Wire reordering is most effective when there is a mix of driver strengths  65 nanometer technology, A=3  m, L=500  m 0 5 10 15 20 123456 Number of weak drivers in a channel of 7 wires Delay improvement, % Average delay minimization Critical delay minimization  Delay improvement: from worst ordering to best ordering

47. 47 Impact of the range of driver strengths

48. 48 Conclusions on wire reordering  It is yet another degree of freedom!  Can help if there is a mix of driver strengths  Don’t try permutations…. Use Symmetric Hill

49. 49 Can we use wire sizing and spacing to reduce power?

50. 50 Dynamic Power breakdown Interconnect Diffusion Gate Technology generation [μm] Source: Nir Magen, SLIP04 ITRS 2001 Edition adapted data The interconnect power problem

51. 51 Interconnect power  Interconnect switching power:  Coupling capacitance:  allocate large spaces to wires with high activity!

52. 52 Interconnect Power Breakdown  Interconnect consumes 50% of dynamic power  Clock power ~40% (of Interconnect and total)  90% of power consumed by 10% of nets Total powerInterconnect power Local clock Local signals * N. Magen, A. Kolodny, U. Weiser and N. Shamir, “ Interconnect-power dissipation in a Microprocessor,” SLIP 2004.

53. 53 Results of spacing experiment Average saving results : 14.3% for ASIC blocks 1 Downsize saving Router saving Average 1 - Estimated based on clock interconnect power * N. Magen, A. Kolodny, U. Weiser and N. Shamir, “ Interconnect-power dissipation in a Microprocessor,” SLIP 2004.

54. 54 Wire reordering for power?  Use Symmetric Hill odrer according to activity factors of the signals? LSiSi S i+1 C i-1 CiCi C i+1 V cc A

55. 55 Conclusions on interconnect power

56. 56 Optimization of drivers and wires together?

57. 57 Optimizing the drivers and wires together?

58. 58 “Logic Gates as Repeaters” (LGR) Idea  Distribute gates over the wire – each gate drives a segment * M. Moreinis, A. Morgenshtein, I. Wagner and A. Kolodny, “Logic gates as Repeaters,” IEEE Transactions on VLSI, 2006.

59. 59 Gate Delay – Logical Effort Total Delay Wire Delay – Elmore LGR Delay Modeling

60. 60 Optimal segmenting

61. 61  Wire length -1200 µm Un-optimized  1.6 nsec Repeater Insertion  0.42 nsec K=5, s inv =43 LGR+Repeters  0.2 nsec s 1 =×16, s 2 =×12, s 3 =×25, s inv =×48, K=2 L 1 =0µm, L 2 =120µm, L 3 =160µm, L inv =480µm, Example: LGR + Repeater Insertion

62. 62 More work to do  Treat gate sizing and wire optimizations together!  Interesting issues for future research:  Signal correlations  Minimizing impact of crosstalk  Timing / power / noise interactions

63. 63 Summary Sizing and spacing of uniform bus wires Sizing and spacing individual wires Wire reordering Speed and Power improvements Optimizing drivers and wires together Future convergence of these techniques?